E. Marinissen

Most-cited papers

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs
E. Marinissen
2012Design, Automation and Test in Europe88 citations
Semantic Scholar
Device-Aware Test: A New Test Approach Towards DPPB Level
M. Fieback, Lizhou Wu, G. Medeiros, H. Aziza +4 more
2019International Test Conference52 citations Open access
Semantic Scholar
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs
E. Marinissen, T. McLaurin, Hailong Jiao
2016IEEE European Test Symposium50 citations Open access
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A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
E. Marinissen, Chun-Chuan Chi, M. Konijnenburg, J. Verbree
2012Journal of electronic testing46 citations Open access
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DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
Sergej Deutsch, B. Keller, V. Chickermane, Subhasish Mukherjee +6 more
20122012 IEEE International Test Conference41 citations
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Electrical Modeling of STT-MRAM Defects
Lizhou Wu, M. Taouil, S. Rao, E. Marinissen +1 more
2018International Test Conference40 citations
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Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface
E. Marinissen, B. De Wachter, Ken Smith, Jorg Kiesewetter +2 more
2014International Test Conference31 citations
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IoT: Source of test challenges
E. Marinissen, Y. Zorian, M. Konijnenburg, Chih-Tsun Huang +10 more
2016IEEE European Test Symposium30 citations Open access
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Defect and Fault Modeling Framework for STT-MRAM Testing
Lizhou Wu, S. Rao, M. Taouil, G. Medeiros +4 more
2021IEEE Transactions on Emerging Topics in Computing28 citations Open access
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Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing
Lizhou Wu, S. Rao, G. Medeiros, M. Taouil +5 more
2019IEEE European Test Symposium27 citations
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Test-station for flexible semi-automatic wafer-level silicon photonics testing
J. De Coster, P. De Heyn, M. Pantouvaki, B. Snyder +5 more
2016IEEE European Test Symposium24 citations
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At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic
K. Shibin, V. Chickermane, B. Keller, C. Papameletis +1 more
2015Asian Test Symposium23 citations
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Using 3D-COSTAR for 2.5D test cost optimization
M. Taouil, S. Hamdioui, E. Marinissen, S. Bhawmik
2013IEEE International Conference on 3D System Integration21 citations
Semantic Scholar
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers
C. Papameletis, B. Keller, V. Chickermane, S. Hamdioui +1 more
2015IEEE design & test19 citations
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Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests
Lizhou Wu, M. Taouil, S. Rao, E. Marinissen +1 more
2020arXiv.org18 citations
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Defect-Location Identification for Cell-Aware Test
Gao Zhan, Santosh Malagi, E. Marinissen, J. Swenton +2 more
2019Latin American Test Symposium17 citations Open access
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Impact of Magnetic Coupling and Density on STT-MRAM Performance
Lizhou Wu, S. Rao, M. Taouil, E. Marinissen +2 more
2020Design, Automation and Test in Europe15 citations Open access
Semantic Scholar
Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library
Zhan Gao, Santosh Malagi, Min-Chun Hu, J. Swenton +5 more
2019International Test Conference15 citations
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Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
M. Taouil, S. Hamdioui, K. Beenakker, E. Marinissen
2012Journal of electronic testing15 citations Open access
Semantic Scholar
Reflow process optimization for micro-bumps applications in 3D technology
J. Derakhshandeh, Inge De Preter, L. England, D. Schmid +9 more
2014Electronics System-integration Technology Conference14 citations
Semantic Scholar
Vesuvius-3D: A 3D-DfT demonstrator
E. Marinissen, B. De Wachter, S. O'Loughlin, Sergej Deutsch +2 more
2014International Test Conference14 citations
Semantic Scholar
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
Lizhou Wu, S. Rao, M. Taouil, E. Marinissen +2 more
2021International Test Conference13 citations
Semantic Scholar
Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic
M. Taouil, Mahmoud Masadeh, S. Hamdioui, E. Marinissen
2015IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems13 citations
Semantic Scholar
Interconnect test for 3D stacked memory-on-logic
M. Taouil, Mahmoud Masadeh, S. Hamdioui, E. Marinissen
2014Design, Automation and Test in Europe13 citations
Semantic Scholar
Design issues in heterogeneous 3D/2.5D integration
D. Milojevic, P. Marchal, E. Marinissen, G. van der Plas +2 more
2013Asia and South Pacific Design Automation Conference13 citations
Semantic Scholar
A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability
Xugang Cao, Hailong Jiao, E. Marinissen
2021IEEE Transactions on Circuits and Systems - II - Express Briefs12 citations Open access
Semantic Scholar
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Lizhou Wu, S. Rao, M. Taouil, E. Marinissen +2 more
2020International Test Conference12 citations Open access
Semantic Scholar
Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices
Zhan Gao, Min-Chun Hu, J. Swenton, Santosh Malagi +3 more
2019International Test Conference in Asia12 citations
Semantic Scholar
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
C. Papameletis, B. Keller, V. Chickermane, E. Marinissen +1 more
2013IEEE European Test Symposium12 citations
Semantic Scholar
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design
Lizhou Wu, S. Rao, M. Taouil, E. Marinissen +2 more
2022IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems11 citations Open access
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Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis
Francesco Lorenzelli, Zhan Gao, J. Swenton, Santosh Malagi +1 more
2021IEEE European Test Symposium11 citations
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Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages
Po-Yao Chuang, Francesco Lorenzelli, S. Chakravarty, Slimane Boutobza +3 more
2023IEEE International Conference on 3D System Integration10 citations Open access
Semantic Scholar
A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards
E. Marinissen, F. Fodor, Bart De Wächter, Jorg Kiesewetter +2 more
2017International Test Conference in Asia10 citations
Semantic Scholar
Device-Aware Test for Back-Hopping Defects in STT-MRAMs
Si-Cong Yuan, M. Taouil, M. Fieback, H. Xun +5 more
2023Design, Automation and Test in Europe9 citations Open access
Semantic Scholar
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages
Po-Yao Chuang, Francesco Lorenzelli, S. Chakravarty, Cheng-Wen Wu +2 more
2023IEEE VLSI Test Symposium9 citations Open access
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Quality versus cost analysis for 3D Stacked ICs
M. Taouil, S. Hamdioui, E. Marinissen
2014IEEE VLSI Test Symposium9 citations
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Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency
Po-Yao Chuang, Francesco Lorenzelli, E. Marinissen
2023International Test Conference in Asia8 citations
Semantic Scholar
Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs
Lizhou Wu, S. Rao, M. Taouil, E. Marinissen +2 more
2021IEEE transactions on computers8 citations Open access
Semantic Scholar
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults
Min-Chun Hu, Zhan Gao, Santosh Malagi, J. Swenton +4 more
2020IEEE European Test Symposium8 citations
Semantic Scholar
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers
Yu LI, Ming Shao, Hailong Jiao, A. Cron +2 more
2018IEEE European Test Symposium8 citations Open access
Semantic Scholar
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
E. Marinissen, F. Fodor, A. Podpod, M. Stucchi +2 more
2018International Test Conference8 citations
Semantic Scholar
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching
M. Taouil, S. Hamdioui, E. Marinissen
2015TODE8 citations
Semantic Scholar
Automated testing of bare die-to-die stacks
E. Marinissen, B. De Wachter, Teng Wang, Jens Fiedler +2 more
2015International Test Conference8 citations
Semantic Scholar
HIGH DENSITY AND HIGH BANDWIDTH CHIP-TO-CHIP CONNECTIONS WITH 20μm PITCH FLIP-CHIP ON FAN-OUT WAFER LEVEL PACKAGE
A. Podpod, D. Velenis, A. Phommahaxay, P. Bex +6 more
20182018 International Wafer Level Packaging Conference (IWLPC)7 citations
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Automatic generation of in-circuit tests for board assembly defects
Harm van Schaaijk, M. Spierings, E. Marinissen
2018IEEE European Test Symposium7 citations Open access
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Processing active devices on Si interposer and impact on cost
D. Velenis, M. Detalle, G. Hellings, M. Scholz +6 more
2015IEEE International Conference on 3D System Integration7 citations
Semantic Scholar
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base
Chun-Chuan Chi, E. Marinissen, S. Goel, Cheng-Wen Wu
2014IEEE Transactions on Very Large Scale Integration (VLSI) Systems7 citations
Semantic Scholar
Cost components for 3D system integration
D. Velenis, M. Detalle, S. Van Huylenbroeck, A. Jourdain +8 more
2014Electronics System-integration Technology Conference7 citations
Semantic Scholar
Si interposer build-up options and impact on 3D system cost
D. Velenis, M. Detalle, E. Marinissen, E. Beyne
2013IEEE International Conference on 3D System Integration7 citations
Semantic Scholar
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
Urban Ingelsson, S. Goel, E. Larsson, E. Marinissen
2015IEEE transactions on computers6 citations
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