V. Chickermane

Most-cited papers

An optimization based approach to the partial scan design problem
V. Chickermane, J. Patel
1990Proceedings. International Test Conference 1990139 citations
Semantic Scholar
Channel masking synthesis for efficient on-chip test compression
V. Chickermane, Brian Foutz, B. Keller
20042004 International Conferce on Test113 citations
Semantic Scholar
A fault oriented partial scan design approach
V. Chickermane, J. Patel
19911991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers108 citations
Semantic Scholar
Non-Scan Design-for-Testability Techniques for Sequential Circuits
V. Chickermane, E. Rudnick, P. Banerjee, J. Patel
199330th ACM/IEEE Design Automation Conference51 citations
Semantic Scholar
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study
S. Goel, S. Adham, Min-Jer Wang, Ji-Jan Chen +12 more
2013International Test Conference46 citations
Semantic Scholar
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
Sergej Deutsch, B. Keller, V. Chickermane, Subhasish Mukherjee +6 more
20122012 IEEE International Test Conference41 citations
Semantic Scholar
Addressing design for testability at the architectural level
V. Chickermane, Jaushin Lee, J. Patel
1994IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.38 citations
Semantic Scholar
Capture power reduction using clock gating aware test generation
K. Chakravadhanula, V. Chickermane, B. Keller, Patrick R. Gallagher +1 more
2009International Test Conference32 citations
Semantic Scholar
Design for Testability Using Architectural Descriptions
V. Chickermane, Jaushin Lee, J. Patel
1992Proceedings International Test Conference 199231 citations
Semantic Scholar
A building block BIST methodology for SOC designs: a case study
Patrick R. Gallagher, V. Chickermane, Steven Gregor, Thomas St. Pierre
2001Proceedings International Test Conference 2001 (Cat. No.01CH37260)29 citations
Semantic Scholar
An observability enhancement approach for improved testability and at-speed test
E. Rudnick, V. Chickermane, J. Patel
1994IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.25 citations
Semantic Scholar
An economic analysis and ROI model for nanometer test
B. Keller, M. Tegethoff, Thomas Bartenstein, V. Chickermane
20042004 International Conferce on Test24 citations
Semantic Scholar
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic
K. Shibin, V. Chickermane, B. Keller, C. Papameletis +1 more
2015Asian Test Symposium23 citations
Semantic Scholar
Automation of 3D-DfT Insertion
Sergej Deutsch, V. Chickermane, B. Keller, Subhasish Mukherjee +3 more
2011Asian Test Symposium22 citations
Semantic Scholar
Advancing test compression to the physical dimension
K. Chakravadhanula, V. Chickermane, P. Cunningham, Brian Foutz +5 more
2017International Test Conference21 citations
Semantic Scholar
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs
V. Chickermane, Patrick R. Gallagher, J. Sage, Paul Yuan +1 more
20082008 IEEE International Test Conference21 citations
Semantic Scholar
A comparative study of design for testability methods using high-level and gate-level descriptions
V. Chickermane, Jaushin Lee, J. Patel
1992IEEE/ACM International Conference on Computer-Aided Design21 citations
Semantic Scholar
SmartScan - Hierarchical test compression for pin-limited low power designs
K. Chakravadhanula, V. Chickermane, D. Pearl, A. Garg +3 more
2013International Test Conference20 citations
Semantic Scholar
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers
C. Papameletis, B. Keller, V. Chickermane, S. Hamdioui +1 more
2015IEEE design & test19 citations
Semantic Scholar
Probe point insertion for at-speed test
E. Rudnick, V. Chickermane, J. Patel
1992Digest of Papers. 1992 IEEE VLSI Test Symposium15 citations
Semantic Scholar
Efficient testing of hierarchical core-based SOCs
B. Keller, K. Chakravadhanula, Brian Foutz, V. Chickermane +5 more
2014International Test Conference13 citations
Semantic Scholar
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
C. Papameletis, B. Keller, V. Chickermane, E. Marinissen +1 more
2013IEEE European Test Symposium12 citations
Semantic Scholar
Sequential circuit testability enhancement using a nonscan approach
E. Rudnick, V. Chickermane, P. Banerjee, J. Patel
1995IEEE Transactions on Very Large Scale Integration (vlsi) Systems11 citations
Semantic Scholar
Test Generation for State Retention Logic
K. Chakravadhanula, V. Chickermane, B. Keller, Patrick R. Gallagher +1 more
2008Asian Test Symposium10 citations
Semantic Scholar
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression
Hiroyuki Nakamura, Akio Shirokane, Y. Nishizaki, Anis Uzzaman +4 more
2005Asian Test Symposium9 citations
Semantic Scholar
Low cost at-speed testing using On-Product Clock Generation compatible with test compression
B. Keller, K. Chakravadhanula, Brian Foutz, V. Chickermane +5 more
20102010 IEEE International Test Conference7 citations
Semantic Scholar
Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
C. Papameletis, V. Chickermane, Brian Foutz, Sarthak Singhal +1 more
2019International Test Conference6 citations
Semantic Scholar
Design and synthesis for testability using architectural descriptions
V. Chickermane
19936 citations
Semantic Scholar
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults
I. Pomeranz, V. Chickermane, S. Venkataraman
2019IEEE VLSI Test Symposium5 citations
Semantic Scholar
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?
K. Chakravadhanula, V. Chickermane, B. Keller, Patrick R. Gallagher +1 more
2009Asian Test Symposium5 citations
Semantic Scholar
System-on-Chip Testability Using LSSD Scan Structures
Kamran Zarrineh, S. Upadhyaya, V. Chickermane
2001IEEE Design & Test of Computers5 citations
Semantic Scholar
Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis
Sanae Seike, Ken Namura, Y. Ohya, Anis Uzzaman +6 more
2006Asian Test Symposium4 citations
Semantic Scholar
Impact of high level functional constraints on testability
Jaushin Lee, V. Chickermane, J. Patel
1993Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium4 citations
Semantic Scholar
APT: an area-performance-testability driven placement algorithm
Sungho Kim, P. Banerjee, V. Chickermane, J. Patel
1992[1992] Proceedings 29th ACM/IEEE Design Automation Conference4 citations
Semantic Scholar
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices
S. Ravi, V. Chickermane, K. Chakravadhanula
2014International Conference on VLSI Design3 citations
Semantic Scholar
PPA Optimization of Test Points in Automotive Designs
Brian Foutz, S. Singhal, P. K. Rai, K. Chakravadhanula +5 more
2022International Test Conference2 citations
Semantic Scholar
Automating IEEE 1500 Core Test—An EDA Perspective
K. Chakravadhanula, V. Chickermane
2009IEEE Design & Test of Computers2 citations
Semantic Scholar
3D Design‐for‐Test Architecture
Erik Jan Marinissen, M. Konijnenburg, J. Verbree, Chun-Chuan Chi +7 more
2019Handbook of 3D Integration1 citations
Semantic Scholar
Unified Compression and LBIST in a Physically Aware Environment
C. Papameletis, V. Chickermane
20191 citations
Semantic Scholar
Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology
Brian Foutz, V. Chickermane, Bing-Hung Li, Harry Linzer +1 more
2006Asian Test Symposium1 citations
Semantic Scholar
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs
Anis Uzzaman, B. Keller, V. Chickermane
2006Asian Test Symposium1 citations
Semantic Scholar
Practical Aspects of Delay Testing for Nanometer Chips
V. Chickermane, B. Keller, Kevin McCauley, Anis Uzzaman
2005Asian Test Symposium1 citations
Semantic Scholar
Integrating logic BIST in VLSI designs with embedded memories
V. Chickermane, S. Richter, C. Barnhart
2000Proceedings of the ... IEEE VLSI Test Symposium1 citations
Semantic Scholar
Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium
Stefano Di Carlo, P. Song, V. Chickermane
2020IEEE design & test0 citations Open access
Semantic Scholar
Innovative practices session 1C: Existing/emerging low power techniques
Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, N. Mukherjee +1 more
2014IEEE VLSI Test Symposium0 citations
Semantic Scholar
International TestConference 2008 Technical Program Committee
R. Aitken, A. Ambler, Y. Asao, K. Butler +20 more
20080 citations
Semantic Scholar
Low Power Reduced Pin Count Test Methodology
K. Chakravadhanula, N. Parimi, Brian Foutz, Bing-Hung Li +1 more
2007Asian Test Symposium0 citations
Semantic Scholar
Facilitating Low Power Scan Test in RTL Compiler
V. Chickermane, S. Bhatia
20060 citations
Semantic Scholar
IEEE Computer Society TTTC: Test Technology Technical Council
E. McCluskey, S. Mitra, N. Wehn, M. Lubaszewski +18 more
2005IEEE International Symposium on On-Line Testing and Robust System Design0 citations
Semantic Scholar
Implementation of Micropipelines in Enablemisable CMOS Differential Logic
V. Chickermane, J. Patel
19950 citations
Semantic Scholar