Chun-Chuan Chi

Most-cited papers

1. 3D DfT architecture for pre-bond and post-bond testing

   E. Marinissen, Chun-Chuan Chi, J. Verbree, M. Konijnenburg

   2010IEEE International Conference on 3D System Integration78 citations

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2. Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base

   Chun-Chuan Chi, E. Marinissen, S. Goel, Cheng-Wen Wu

   20112011 IEEE International Test Conference52 citations

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3. 3D-IC interconnect test, diagnosis, and repair

   Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin

   2013IEEE VLSI Test Symposium48 citations

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4. A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

   E. Marinissen, Chun-Chuan Chi, M. Konijnenburg, J. Verbree

   2012Journal of electronic testing46 citations Open access

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5. DfT Architecture for 3D-SICs with Multiple Towers

   Chun-Chuan Chi, E. Marinissen, S. Goel, Cheng-Wen Wu

   20112011 Sixteenth IEEE European Test Symposium34 citations

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6. Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base

   Chun-Chuan Chi, E. Marinissen, S. Goel, Cheng-Wen Wu

   2011Asian Test Symposium15 citations

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7. 3D-IC BISR for stacked memories using cross-die spares

   Chun-Chuan Chi, Yung-Fa Chou, D. Kwai, Yu-Ying Hsiao +4 more

   2012Proceedings of Technical Program of 2012 VLSI Design, Automation and Test11 citations

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8. On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs

   Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang +2 more

   2014IEEE design & test8 citations

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9. Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base

   Chun-Chuan Chi, E. Marinissen, S. Goel, Cheng-Wen Wu

   2014IEEE Transactions on Very Large Scale Integration (VLSI) Systems7 citations

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10. A low-cost and scalable test architecture for multi-core chips

    Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li

    2010IEEE European Test Symposium6 citations

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11. Test Integration for SOC Supporting Very Low-Cost Testers

    Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu

    2009Asian Test Symposium4 citations

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12. A low-cost wireless interface with no external antenna and crystal oscillator for Cm-range contactless testing

    Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang +15 more

    2011Design Automation Conference3 citations

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13. 3D Design‐for‐Test Architecture

    Erik Jan Marinissen, M. Konijnenburg, J. Verbree, Chun-Chuan Chi +7 more

    2019Handbook of 3D Integration1 citations

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14. 3D-IC BISR for stacked memories using cross-die spares

    Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao +4 more

    2012Proceedings of Technical Program of 2012 VLSI Design, Automation and Test0 citations

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15. A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

    E. Marinissen, Chun-Chuan Chi, M. Konijnenburg, J. Verbree

    2011Journal of electronic testing0 citations Open access

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