J. Warnock

Most-cited papers

The design and implementation of a first-generation CELL processor
D. Pham, S. Asano, M. Bolliger, M. N. Day +16 more
2005ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.605 citations Open access
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Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
D. Pham, T. Aipperspach, D. Boerstler, M. Bolliger +21 more
2006IEEE Journal of Solid-State Circuits264 citations
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Physical design of a fourth-generation POWER GHz microprocessor
C. Anderson, J. Petrovick, J. Keaty, J. Warnock +21 more
20012001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)124 citations
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A VLSI-compatible high-speed silicon photodetector for optical data link applications
M. Ghioni, F. Zappa, V. Kesan, J. Warnock
199698 citations
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A Room Temperature 0.1 /spl mu/m CMOS on SOI
G. Shahidi, C. Blair, K. Beyer, T. Bucelot +25 more
1993Symposium on VLSI Technology76 citations
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A 400 MHz S/390 microprocessor
Charles F. Webb, C. Anderson, L. Sigal, K. Shepard +19 more
19971997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers61 citations
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Circuit design challenges at the 14nm technology node
J. Warnock
2011Design Automation Conference58 citations
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POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor
D. Wendel, R. Kalla, J. Warnock, Robert Cargnoni +20 more
2011IEEE Journal of Solid-State Circuits54 citations
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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking
Eric Fluhr, S. Baumgartner, D. Boerstler, J. Bulzacchelli +26 more
2015IEEE Journal of Solid-State Circuits50 citations
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Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors
J. Burghartz, Y.-C. J. Sun, C. Stanis, S. Mader +1 more
199250 citations
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Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology
J. Comfort, G. Patton, J. Cressler, Woo-hyeong Lee +12 more
1990International Technical Digest on Electron Devices46 citations
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Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System
J. Warnock, Y. Chan, S. Carey, H. Wen +15 more
2012IEEE Journal of Solid-State Circuits39 citations
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CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications
G. Shahidi, J. Warnock, J. Comfort, S. Fischer +10 more
1995IBM Journal of Research and Development39 citations
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50-GHz self-aligned silicon bipolar transistors with ion-implanted base profiles
J. Warnock, J. Cressler, Keith A. Jenkins, T.-C. Chen +2 more
1990IEEE Electron Device Letters38 citations
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Silicon bipolar device structures for digital applications: technology trends and future directions
J. Warnock
199535 citations
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A 5.2GHz microprocessor chip for the IBM zEnterprise™ system
J. Warnock, Y. Chan, W. Huott, S. Carey +23 more
2011IEEE International Solid-State Circuits Conference33 citations
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A High Performance 0.25/spl mu/m CMOS
C. G. Shahidi, J. Warnock, A. Acovic, P. Agnello +24 more
1993Symposium on VLSI Technology33 citations
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High-performance devices for a 0.15- mu m CMOS technology
Ghavam G. Shahidi, J. Warnock, S. Fischer, P. McFarland +8 more
1993IEEE Electron Device Letters32 citations
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Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing
Ghavam G. Shahidi, B. Davari, Y. Taur, J. Warnock +10 more
1990International Technical Digest on Electron Devices31 citations
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4.1 22nm Next-generation IBM System z microprocessor
J. Warnock, B. Curran, John Badar, G. Fredeman +27 more
2015IEEE International Solid-State Circuits Conference30 citations
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Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
J. Warnock, Y. Chan, H. Harrer, S. Carey +21 more
2014IEEE Journal of Solid-State Circuits29 citations
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A high-speed complementary silicon bipolar technology with 12-fJ power-delay product
J. Cressler, J. Warnock, D. Harame, Joachim N. Burghartz +2 more
1993IEEE Electron Device Letters28 citations
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POWER7TM local clocking and clocked storage elements
J. Warnock, L. Sigal, D. Wendel, K. Muller +4 more
2010IEEE International Solid-State Circuits Conference26 citations
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Cell Broadband Engine processor: Design and implementation
Mack W. Riley, J. Warnock, D. Wendel
2007IBM Journal of Research and Development23 citations Open access
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Multigigahertz voltage-controlled oscillators in advanced silicon bipolar technology
M. Soyuer, J. Warnock
1992IEEE J. Solid State Circuits23 citations
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Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor
L. Sigal, J. Warnock, B. Curran, Y. Chan +7 more
1997IBM Journal of Research and Development22 citations
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Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
D. Pham, H. Anderson, E. Behnen, M. Bolliger +19 more
2006Asia and South Pacific Conference on Design Automation, 2006.21 citations
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The design methodology and implementation of a first-generation CELL processor: a multi-core SoC
D. Pham, E. Behnen, M. Bolliger, H. Hofstee +14 more
2005Proceedings of the IEEE Custom Integrated Circuits Conference21 citations
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55 Ghz Polysilicon-Emitter Graded Sige-Base Pnp Transistors
D. Harame, B. Meyerson, Emmanuel F. Crabbe, C. Stanis +9 more
1991Symposium on VLSI Technology21 citations
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Cell processor low-power design methodology
D. Stasiak, Rajat Chaudhry, D. Cox, S. Posluszny +4 more
2005IEEE Micro20 citations
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Sub-30ps ECL circuits using high-f/sub T/ Si and SiGe epitaxial base SEEW transistors
Joachim N. Burghartz, J. Comfort, G. Patton, J. Cressler +10 more
1990International Technical Digest on Electron Devices20 citations
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The zEnterprise 196 System and Microprocessor
B. Curran, Lee Eisen, E. Schwarz, Pak-Kin Mak +3 more
2011IEEE Micro17 citations
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The design and optimization of high-performance, double-poly self-aligned p-n-p technology
Pong-Fei Lu, J. Warnock, J. Cressler, K. Jenkins +1 more
199117 citations
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Use of electron-beam irradiation to study performance degradation of bipolar transistors after reverse-bias stress
K. Jenkins, J. Cressler, J. Warnock
1991International Electron Devices Meeting 1991 [Technical Digest]17 citations
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IBM z14™: 14nm microprocessor for the next-generation mainframe
C. Berry, J. Warnock, John Isakson, John Badar +21 more
2018IEEE International Solid-State Circuits Conference16 citations
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5.5GHz system z microprocessor and multi-chip module
J. Warnock, Y. Chan, H. Harrer, D. L. Rude +19 more
20132013 IEEE International Solid-State Circuits Conference Digest of Technical Papers16 citations
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An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects
R. Kanj, R. Joshi, Chad Adams, J. Warnock +1 more
2009IEEE/ACM International Conference on Computer-Aided Design16 citations
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IBM POWER8 circuit design and energy optimization
V. Zyuban, J. Friedrich, D. Dreps, J. Pille +19 more
2015IBM Journal of Research and Development15 citations
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SE2 when processors hit the power wall (or "when the CPU hits the fan")
S. Naffziger, J. Warnock, H. Knapp
2005ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.15 citations
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Partial-SOI isolation structure for reduced bipolar transistor parasitics
Joachim N. Burghartz, J. Cressler, J. Warnock, R. Mcintosh +7 more
1992IEEE Electron Device Letters15 citations
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Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor
J. Warnock, D. Wendel, T. Aipperspach, E. Behnen +10 more
2006IEEE Journal of Solid-State Circuits14 citations
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High Performance Complementary Bipolar Technology
J. Warnock, J. Cressler, J. Burghartz, D. Harame +2 more
1993Symposium on VLSI Technology14 citations
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High-performance bipolar technology for improved ECL power delay
J. Warnock, J. Cressler, Keith A. Jenkins, C. Stanis +4 more
1991IEEE Electron Device Letters14 citations
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Off-state self-heating, micro-hot-spots, and stress-induced device considerations in scaled technologies
Siyu Koswatta, Narasimha R. Mavilla, Mohit Bajaj, J. Johnson +13 more
2015International Electron Devices Meeting13 citations
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A scaled 0.25- mu m bipolar technology using full e-beam lithography
J. Cressler, J. Warnock, P. Coane, K. Chiong +10 more
1992IEEE Electron Device Letters13 citations
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A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar
Ghavam G. Shahidi, J. Warnock, B. Davari, B. Wu +14 more
19921992 Symposium on VLSI Technology Digest of Technical Papers13 citations
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IBM z14 design methodology enhancements in the 14-nm technology node
C. Berry, J. Warnock, John Badar, Dean G. Bair +17 more
2018IBM Journal of Research and Development12 citations
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Scaling the silicon bipolar transistor for sub-100-ps ECL circuit operation at liquid nitrogen temperature
J. Cressler, T.-C. Chen, J. Warnock, Denny D. Tang +1 more
199012 citations
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Circuit and PD challenges at the 14nm technology node
J. Warnock
2013ACM International Symposium on Physical Design9 citations
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Design, CAD and technology challenges for future processors: 3D perspectives
Jeff Burns, G. Carpenter, Eren Kursun, R. Puri +2 more
2011Design Automation Conference9 citations
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