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T. Slegel · SciRah

Researcher profile · Semantic Scholar

T. Slegel

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T. Slegel — researcher profile on SciRah

h-index: 10
Works: 33
Citations: 838

Most-cited papers

IBM's S/390 G5 microprocessor design
T. Slegel, R. Averill, M. Check, Bruce C. Giamei +10 more
1999IEEE Micro356 citations
Semantic Scholar
Transactional Memory Architecture and Implementation for IBM System Z
C. Jacobi, T. Slegel, D. Greiner
2012Micro162 citations
Semantic Scholar
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities
Ramon Bertran, A. Buyuktosunoglu, P. Bose, T. Slegel +4 more
2014Micro75 citations
Semantic Scholar
A 400 MHz S/390 microprocessor
Charles F. Webb, C. Anderson, L. Sigal, K. Shepard +19 more
19971997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers61 citations
Semantic Scholar
Custom S/390 G5 and G6 microprocessors
M. Check, T. Slegel
1999IBM Journal of Research and Development56 citations
Semantic Scholar
The IBM eServer z990 microprocessor
T. Slegel, Erwin Pfeffer, Jeffrey A. Magee
2004IBM Journal of Research and Development46 citations
Semantic Scholar
Robust power management in the IBM z13
Tobias Webel, Preetham Lobo, Ramon Bertran, G. Salem +11 more
2015IBM Journal of Research and Development25 citations
Semantic Scholar
The design of the fixed point unit for the z990 microprocessor
F. Busaba, T. Slegel, S. Carlough, C. Krygowski +1 more
2004ACM Great Lakes Symposium on VLSI22 citations
Semantic Scholar
Design and performance of the IBM Enterprise System/9000 Type 9121 Vector Facility
T. Slegel, Robert J. Veracca
1991IBM Journal of Research and Development20 citations
Semantic Scholar
IBM System z9 eFUSE applications and methodology
R. Rizzolo, Thomas G. Foote, J. Crafts, David A. Grosch +7 more
2007IBM Journal of Research and Development13 citations
Semantic Scholar
Exploiting Multiple Vt and Copper Interconnects
T. McPherson, R. Averill, D. Balazich, K. Barkley +18 more
20001 citations
Semantic Scholar
A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders
Charles F. Webb, C. Anderson, L. Sigal, K. Shepard +19 more
1997IEEE J. Solid State Circuits1 citations
Semantic Scholar
Design and verification of DEFLATE acceleration as an architected instruction in z15
M. Klein, A. Misra, Bülent Abali, Puja Sethia +4 more
2020IBM Journal of Research and Development0 citations
Semantic Scholar
Identifying processor attributes based on detecting a guarded storage event
D. Greiner, C. Jacobi, Marcel Mitran, Volodymyr Paprotski +2 more
20170 citations
Semantic Scholar
For early access sensitive transaction-bound memory
M. Gschwind, V. Salapura, C. Shum, T. Slegel
20160 citations
Semantic Scholar
Instructions "Vector generate mask"
Jonathan D. Bradbury, T. Slegel, E. Schwarz, R. Enenkel
20130 citations
Semantic Scholar
Traitement de transaction
D. Greiner, Christian Jacobi, T. Slegel
20130 citations
Semantic Scholar
Instruction d'abandon de transaction
D. Greiner, Christian Jacobi, T. Slegel, Marcel Mitran
20130 citations
Semantic Scholar
Non-transaction-oriented storage instruction
D. Greiner, C. Jacobi, T. Slegel
20120 citations
Semantic Scholar
Performance innovation in the IBM zEnterprise 196 processor
D. Greiner, Marcel Mitran, T. Slegel, C. R. Walters +1 more
2012IBM Journal of Research and Development0 citations
Semantic Scholar
IBM zEnterpriseTM energy efficient 5.2Ghz processor chip
H. Wen, J. Warnock, Y. Chan, G. Mayer +13 more
20112011 IEEE International Conference on IC Design & Technology0 citations
Semantic Scholar
Facility for extracting the cache attributes and instruction thereto
D. Greiner, T. Slegel
20090 citations
Semantic Scholar
Speicherinvalidierung, deletion of buffer entries
T. Slegel, L. Heller, Erwin Pfeffer, K. Plambeck
20040 citations
Semantic Scholar
Invalidating storage, clearing entries from the buffer.
L. Heller, Erwin Pfeffer, K. Plambeck, T. Slegel
20040 citations
Semantic Scholar
Ugyldiggörelse of a warehouse and deleting bufferindlæsninger
T. Slegel, L. Heller, Erwin Pfeffer, K. Plambeck
20040 citations
Semantic Scholar
Invalidation of memory entries, deleting cache entries
L. Heller, Erwin Pfeffer, K. Plambeck, T. Slegel
20040 citations
Semantic Scholar
A method for processing a computer command, with pre-recorded offset
M. Check, T. Slegel, B. Moore
20040 citations
Semantic Scholar
Invalidating entries in a Page Table
T. Slegel, L. Heller, Erwin Pfeffer, K. Plambeck
20040 citations
Semantic Scholar
Invalidation of storage, deleting puffeindgange
T. Slegel, L. Heller, Erwin Pfeffer, K. Plambeck
20040 citations
Semantic Scholar
Ugyldiggörelse of storage and resetting of the buffer entries
T. Slegel, L. Heller, Erwin Pfeffer, K. Plambeck
20040 citations
Semantic Scholar
System for transmitting data
Donald H. Friedberg, K. D. Lamb, C. Reed, T. Slegel +4 more
19930 citations
Semantic Scholar
Vector processing architecture for block digital signal processors
T. Slegel, K. Mondal
19830 citations
Semantic Scholar
The hardware implementation of block digital filters.
T. Slegel
19820 citations
Semantic Scholar

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