H. Niiyama

Improved Electron-Beam / DUV Intra-Level Mix-and-Match As A Production Viable Lithography With 100-nm Resolution

Shunko Magoshi, H. Niiyama, Shinji Sato, Y. Kato +7 more

1998Digest of Papers. Microprocesses and Nanotechnology'98. 198 International Microprocesses and Nanotechnology Conference (Cat. No.98EX135)1 citations

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H. Niiyama

Most-cited papers

High-performance 0.10- mu m CMOS devices operating at room temperature

Hot-carrier effects in 0.1 mu m gate length CMOS devices

Silicon-Based Single-Electron-Tunneling Transistor Operated at 4.2 K

Inverter performance of 0.10 /spl mu/m CMOS operating at room temperature

Performance fluctuations of 0.10 /spl mu/m MOSFETs-limitation of 0.1 /spl mu/m ULSIs

A High-Performance 0.05 µm SOI MOS FET: Possibility of Velocity Overshoot

Improvement of P–N Junction Leakage and Reduction in Interface State Density in Transistors by Cryo Implantation Technology

Ultralow Contact Resistivity for a Metal/p-Type Silicon Interface by High-Concentration Germanium and Boron Doping Combined with Low-Temperature Annealing

Improved Electron-Beam/Deep-Ultraviolet Intralevel Mix-and-Match Lithography with 100 nm Resolution

High Speed 0.1 μm CMOS Devices Operating at Room Temperature

Reduction of surface roughness and defect density by cryogenic implantation of arsenic

Optimization of a High-Performance Chemically Amplified Positive Resist for Electron-Beam Lithography

Ultra-low Contact Resistivity by High Concentration Germanium and Boron Ion Implantation Combined with Low Temperature Annealing

0.25 /spl mu/m gate length CMOS devices for cryogenic operation

Impact of Contact Resistance and Junction Capacitance on the Switching Performance in Scaled 0.1μm CMOS Devices

Proximity effect correction on the multilevel interconnect metal for high-energy electron-beam lithography

Sub-20 psec Switching CMOS at Liquid N2 Temperature

Improved Electron-Beam / DUV Intra-Level Mix-and-Match As A Production Viable Lithography With 100-nm Resolution

0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth technique

0.228 /spl mu/m/sup 2/ trench cell technologies with bottle-shaped capacitor for 1 Gbit DRAMs

Anomalous Resistance in O . Ipm-Region Ti-Siticided Poty Si Gate

A High-Performance 0.05 µm SOI MOS FET: Possibility of Velocity Overshoot

Optimization of a High-Performance Chemically Amplified Positive Resist for Electron-Beam Lithography

A High Performance 0.05μm MOSFET with Thin SOI/Buried Oxide Structure

Silicon-Based Single-Electron-Tunneling Transistor Operated at 4.2 K

The Role of the Residual Solvent for Chemical Amplification Resists