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Takuji Matsumoto · SciRah

Researcher profile · Semantic Scholar

Takuji Matsumoto

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Takuji Matsumoto — researcher profile on SciRah

h-index: 6
Works: 28
Citations: 132

Most-cited papers

Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications
Takuji Matsumoto, S. Maeda, H. Dang, T. Uchida +9 more
2002Digest. International Electron Devices Meeting,25 citations
Semantic Scholar
Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology
Y. Hirano, Takuji Matsumoto, S. Maeda, Toshiaki Iwamatsu +7 more
2000International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)24 citations
Semantic Scholar
Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application
Y. Hirano, Takashi Ipposhi, H. Dang, Takuji Matsumoto +10 more
2003IEEE International Electron Devices Meeting 200321 citations
Semantic Scholar
Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications
S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki +9 more
200120 citations
Semantic Scholar
70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications
Takuji Matsumoto, S. Maeda, K. Ota, Y. Hirano +11 more
2001International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)19 citations
Semantic Scholar
Bulk-layout-compatible 0.18-/spl mu/m SOI-CMOS technology using body-tied partial-trench-isolation (PTI)
Y. Hirano, S. Maeda, Takuji Matsumoto, K. Nii +7 more
20017 citations
Semantic Scholar
Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 /spl mu/m partially depleted SOI MOSFETs
Takuji Matsumoto, S. Maeda, Y. Hirano, K. Eikyu +4 more
20024 citations
Semantic Scholar
Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications
S. Maeda, Y. Wada, K. Yamamoto, H. Komurasaki +9 more
20002000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)4 citations
Semantic Scholar
Improvement of Surface Morphology of Epitaxial Silicon Film for Elevated Source/Drain Ultrathin Silicon-on-Insulator Complementary-Metal-Oxide-Semiconductor Devices
K. Sugihara, T. Nakahata, Takuji Matsumoto, S. Maeda +9 more
20033 citations Open access
Semantic Scholar
Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)
Y. Hirano, S. Maeda, Takuji Matsumoto, K. Nii +7 more
19991999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)3 citations
Semantic Scholar
A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide
S. Maeda, K. Shiga, H. Naruoka, N. Hattori +7 more
20011 citations
Semantic Scholar
Clarification of Floating-Body Effects on Current Drivability in Deep Sub-Quarter Micron Partially-Depleted SOI MOSFET's
Takuji Matsumoto, S. Maeda, Y. Hirano, K. Eikyu +4 more
19991 citations
Semantic Scholar
Wafer Backside Fine Pitch Copper Interconnects and Low-profile Micro-bumps Pad Process for Multiple Chip-on-Wafer Stacking Structure
Syuto Tamura, Junichiro Fujimagari, Yuji Uesugi, Takuji Matsumoto +3 more
2025Electronic Components and Technology Conference0 citations
Semantic Scholar
A semiconductor device manufacturing process and semiconductor wafer
Takuji Matsumoto, M. Tsujiuchi, T. Iwamatsu, S. Maeda +2 more
20030 citations
Semantic Scholar
Low-Noise and High-Frequency 0.10μm body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10Gbps Network LSI
T. Iwamatsu, Mikio Tujiuchi, Y. Hirano, Takuji Matsumoto +11 more
20030 citations
Semantic Scholar
A semiconductor device with reduced Gateüberlappungskapazitanz and method of manufacturing the semiconductor device
Hai Dang, Y. Hirano, S. Maeda, Takuji Matsumoto
20030 citations
Semantic Scholar
Low-Noise and High-Frequency 0 . 10 μ m body-tied SOI-CMOS Technology with High-Resistivity Substrate for Low-Power 10 Gbps Network LSI
T. Iwamatsu, Mikio Tujiuchi, Y. Hirano, Takuji Matsumoto +11 more
20030 citations
Semantic Scholar
Device semiconductor and method of manufacture
Takuji Matsumoto, H. Sayama, S. Maeda
20020 citations
Semantic Scholar
A semiconductor device on itself substrate and method of manufacturing
Takuji Matsumoto, H. Sayama, S. Maeda, T. Iwamatsu +1 more
20020 citations
Semantic Scholar
Elevated Source/Drain Engineering with 0.22-nm-Rms Smooth Surface Morphology for 90-nm-node Ultrathin-SOI CMOS
K. Sugihara, T. Nakahata, Takuji Matsumoto, S. Maeda +9 more
20020 citations
Semantic Scholar
Semiconductor device and method of manufacturing the same, and semiconductor wafer
Y. Hirano, T. Iwamatsu, S. Maeda, Shigeto Maekawa +8 more
20020 citations
Semantic Scholar
semiconductor wafer, manufacturing process and manufacturing apparatus
T. Ipposhi, Takuji Matsumoto
20010 citations
Semantic Scholar
A semiconductor device with combined grave isolation structure in an SOI substrate, and methods for their preparation
T. Ipposhi, T. Iwamatsu, Takuji Matsumoto
20000 citations
Semantic Scholar
Semiconductor chip comprises silicon layer, oxide film and gas-retaining porous silicon layer in sequence
Takuji Matsumoto, T. Iwamatsu
20000 citations
Semantic Scholar
The nonvolatile semiconductor memory device and semiconductor integrated circuit
S. Maeda, T. Kunikiyo, Takuji Matsumoto
20000 citations
Semantic Scholar
A semiconductor device and method of manufacture
T. Iwamatsu, T. Ipposhi, Takuji Matsumoto
20000 citations
Semantic Scholar
A semiconductor device, method for producing the same and method of disposing a dummy area
Takuji Matsumoto, T. Iwamatsu, Y. Hirano
20000 citations
Semantic Scholar
Halbleitereinrichtung mit SOI-Aufbau und Teiltrennbereichen
Yuuichi Hirano, Takashi Ipposhi, T. Iwamatsu, S. Maeda +4 more
19990 citations
Semantic Scholar

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