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K. Kao · SciRah

Researcher profile · Semantic Scholar

K. Kao

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K. Kao — researcher profile on SciRah

h-index: 20
Works: 76
Citations: 1,522

Most-cited papers

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs
K. Kao, A. Verhulst, W. Vandenberghe, B. Sorée +2 more
2012IEEE Transactions on Electron Devices425 citations
Semantic Scholar
Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets
K. Kao, A. Verhulst, W. Vandenberghe, B. Sorée +4 more
2012IEEE Transactions on Electron Devices138 citations
Semantic Scholar
Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors
D. Verreck, A. Verhulst, K. Kao, W. Vandenberghe +2 more
2013IEEE Transactions on Electron Devices58 citations
Semantic Scholar
Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
P. Sung, Shu-Wei Chang, K. Kao, Chien-Ting Wu +6 more
2020IEEE Transactions on Electron Devices49 citations
Semantic Scholar
Counterdoped Pocket Thickness Optimization of Gate-on-Source-Only Tunnel FETs
K. Kao, A. Verhulst, W. Vandenberghe, K. De Meyer
2013IEEE Transactions on Electron Devices48 citations
Semantic Scholar
Reliability Mechanisms of LTPS-TFT With $\hbox{HfO}_{2}$ Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress
Ming-Wen Ma, Chih-Yang Chen, Woei-Cherng Wu, Chun-Jung Su +3 more
2008IEEE Transactions on Electron Devices48 citations
Semantic Scholar
Fabrication and Analysis of a Heterojunction Line Tunnel FET
A. Walke, A. Vandooren, R. Rooyackers, D. Leonelli +11 more
201443 citations
Semantic Scholar
Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET
A. Walke, A. Vandooren, R. Rooyackers, D. Leonelli +11 more
2014IEEE Transactions on Electron Devices43 citations
Semantic Scholar
Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs
Malkundi Puttaveerappa Vijay Kumar, Chia-Ying Hu, K. Kao, Yao-Jen Lee +1 more
2015IEEE Transactions on Electron Devices41 citations
Semantic Scholar
A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing
Yao-Jen Lee, Ta-Chun Cho, K. Kao, P. Sung +15 more
20142014 IEEE International Electron Devices Meeting38 citations
Semantic Scholar
Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures
K. Kao, Tzung-Rang Wu, Hong-lin Chen, Wen-Jay Lee +4 more
2020IEEE Electron Device Letters36 citations
Semantic Scholar
A model determining optimal doping concentration and material's band gap of tunnel field-effect transistors
W. Vandenberghe, A. Verhulst, K. Kao, K. De Meyer +3 more
201235 citations
Semantic Scholar
First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications
Shu-Wei Chang, Tsung-Han Lu, Cong Yang, Cheng-Jui Yeh +37 more
2022IEEE Transactions on Electron Devices33 citations
Semantic Scholar
Tensile strained Ge tunnel field-effect transistors: k · p material modeling and numerical device simulation
K. Kao, A. Verhulst, M. L. Van de Put, W. Vandenberghe +3 more
201431 citations
Semantic Scholar
Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION
Chun-Jung Su, Y.-T. Tang, Y.-C. Tsou, P. Sung +26 more
2017Symposium on VLSI Technology29 citations
Semantic Scholar
Impact of High-$\kappa$ Offset Spacer in 65-nm Node SOI Devices
Ming-Wen Ma, Chien-Hung Wu, Tsung-Yu Yang, K. Kao +4 more
2007IEEE Electron Device Letters25 citations
Semantic Scholar
Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability
Chun-Jung Su, T. Hong, Y.-C. Tsou, Fu-Ju Hou +21 more
2017International Electron Devices Meeting24 citations
Semantic Scholar
High performance poly Si junctionless transistors with sub-5nm conformally doped layers by molecular monolayer doping and microwave incorporating CO2 laser annealing for 3D stacked ICs applications
Yao-Jen Lee, Ta-Chun Cho, P. Sung, K. Kao +24 more
2015International Electron Devices Meeting24 citations
Semantic Scholar
Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors
K. Kao, A. Verhulst, R. Rooyackers, B. Douhard +12 more
201423 citations Open access
Semantic Scholar
Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size
X.-R. Yu, Min-Hui Chuang, S. Chang, W. Chang +27 more
2022International Electron Devices Meeting20 citations
Semantic Scholar
Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology
Yao-Jen Lee, Fu-Ju Hou, S. Chuang, F. Hsueh +19 more
2015International Electron Devices Meeting20 citations
Semantic Scholar
A Dopingless FET With Metal–Insulator–Semiconductor Contacts
K. Kao, Liang-Yu Chen
2017IEEE Electron Device Letters18 citations
Semantic Scholar
Perspective of tunnel-FET for future low-power technology nodes
A. Verhulst, D. Verreck, Q. Smets, K. Kao +10 more
20142014 IEEE International Electron Devices Meeting18 citations
Semantic Scholar
Fluorinated HfO2 gate dielectrics engineering for CMOS by pre- and post-CF4 plasma passivation
Woei-Cherng Wu, Chao-Sung Lai, Shih-Ching Lee, Ming-Wen Ma +10 more
20082008 IEEE International Electron Devices Meeting17 citations
Semantic Scholar
First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)
Taeeun Hong, W. Chang, A. Agarwal, Y.-T. Huang +40 more
2020International Electron Devices Meeting16 citations
Semantic Scholar
Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High- $\kappa$ Gate Dielectric
Ming-Wen Ma, Chih-Yang Chen, Chun-Jung Su, Woei-Cherng Wu +4 more
2008IEEE Electron Device Letters15 citations
Semantic Scholar
Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High-κ Gate Dielectric
Ming-Wen Ma, Woei-Cherng Wu, K. Kao
200815 citations
Semantic Scholar
Device simulations with A U-Net model predicting physical quantities in two-dimensional landscapes
Wen-Jay Lee, Wu-Tsung Hsieh, Bin Fang, K. Kao +1 more
2023Scientific Reports14 citations Open access
Semantic Scholar
Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices
S. Chuang, C. Ta, P. Sung, K. Kao +4 more
201714 citations
Semantic Scholar
First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications
S. Chang, Tsung-Han Lu, C. Yang, Chun-Jui Yeh +37 more
2021International Electron Devices Meeting12 citations
Semantic Scholar
Modeling the impact of junction angles in tunnel field-effect transistors
K. Kao, A. Verhulst, W. Vandenberghe, B. Sorée +2 more
201211 citations
Semantic Scholar
First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering
X.-R. Yu, W. Chang, T. Hong, P. Sung +19 more
20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)10 citations
Semantic Scholar
A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node
Y.-T. Tang, Chun-Jung Su, Y.-S. Wang, K. Kao +11 more
20182018 IEEE Symposium on VLSI Technology10 citations
Semantic Scholar
Undoped and Doped Junctionless FETs: Source/Drain Contacts and Immunity to Random Dopant Fluctuation
Liang-Yu Chen, Yu-Feng Hsieh, K. Kao
2017IEEE Electron Device Letters9 citations
Semantic Scholar
A Simulation Study on Process Sensitivity of a Line Tunnel Field-Effect Transistor
A. Walke, W. Vandenberghe, K. Kao, A. Vandooren +1 more
2013IEEE Transactions on Electron Devices9 citations
Semantic Scholar
Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization
Malkundi Puttaveerappa Vijay Kumar, Chia-Ying Hu, A. Walke, K. Kao +1 more
2017IEEE Transactions on Electron Devices7 citations
Semantic Scholar
Si-based tunnel field-effect transistors for low-power nano-electronics
A. Verhulst, W. Vandenberghe, Daniele Leonelli, R. Rooyackers +14 more
2011Device Research Conference7 citations
Semantic Scholar
Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications
K. Kao, C. Godfrin, A. Elsayed, R. Li +5 more
2022IEEE Electron Device Letters6 citations
Semantic Scholar
3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers
Chun-Jung Su, M.-K. Huang, K. S. Lee, V.-P.-H. Hu +19 more
2020International Electron Devices Meeting6 citations
Semantic Scholar
Junctionless FETs With a Fin Body for Multi- ${V}_{\text{TH}}$ and Dynamic Threshold Operation
Malkundi Puttaveerappa Vijay Kumar, Jer-Yi Lin, K. Kao, Tien-Sheng Chao
2018IEEE Transactions on Electron Devices6 citations
Semantic Scholar
Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- $\kappa$ LTPS-TFT
Ming-Wen Ma, Chih-Yang Chen, Chun-Jung Su, Woei-Cherng Wu +5 more
2008IEEE Electron Device Letters6 citations
Semantic Scholar
First Demonstration of Ferroelectric Tunnel Thin-Film Transistor Nonvolatile Memory With Polycrystalline-Silicon Channel and HfZrO Gate Dielectric
William Cheng-Yu Ma, Chun-Jung Su, K. Kao, Yao-Jen Lee +9 more
2022IEEE Transactions on Electron Devices5 citations
Semantic Scholar
Demonstration of synaptic characteristics of polycrystalline-silicon ferroelectric thin-film transistor for application of neuromorphic computing
William Cheng-Yu Ma, Chun-Jung Su, Yao-Jen Lee, K. Kao +5 more
2022Semiconductor Science and Technology5 citations
Semantic Scholar
Investigation of the passivation-induced VTH shift in p-GaN HEMTs with Au-free gate-first process
Shun-Wei Tang, Zhen-Hong Huang, Yi-Cheng Chen, Cheng-Hung Wu +5 more
2021Microelectronics and reliability5 citations
Semantic Scholar
Impact of the polarization on time-dependent dielectric breakdown in ferroelectric Hf0.5Zr0.5O2 on Ge substrates
Ting-Hsin Yang, Chun-Jung Su, Yu-Shun Wang, K. Kao +2 more
2020Japanese Journal of Applied Physics5 citations
Semantic Scholar
High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $\hbox{TaN/HfO}_{2}$ Gate Stack Structure
Ming-Wen Ma, Tien-Sheng Chao, Chun-Jung Su, Woei-Cherng Wu +2 more
2008IEEE Electron Device Letters5 citations
Semantic Scholar
Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs
Si-Hua Chen, Shang-Wei Lian, Tzung-Rang Wu, Tay-Rong Chang +6 more
2019IEEE Transactions on Electron Devices4 citations
Semantic Scholar
Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation
Kunal Kumar, Yu-Feng Hsieh, J. Liao, K. Kao +1 more
2018IEEE Transactions on Electron Devices4 citations
Semantic Scholar
SiGe band-to-band tunneling calibration based on p-i-n diodes: Fabrication, measurement and simulation
K. Kao, A. Verhulst, R. Rooyackers, A. Hikavyy +14 more
20134 citations Open access
Semantic Scholar
Impacts of high-κ offset spacer on 65-nm node SOI devices
Ming-Wen Ma, Tien-Sheng Chao, K. Kao, Jyun-Siang Huang +1 more
20064 citations
Semantic Scholar

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