Y. Takeyama

Most-cited papers

1. A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver

   O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama +9 more

   2009IEEE International Solid-State Circuits Conference75 citations

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2. A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

   Cuong Trinh, N. Shibata, T. Nakano, M. Ogawa +52 more

   2009IEEE International Solid-State Circuits Conference68 citations

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3. A Process-Variation-Tolerant Dual-Power-Supply SRAM with 0.179μm2 Cell in 40nm CMOS Using Level-Programmable Wordline Driver

   Yuki Fujimura, Osamu Hirabayashi, Kawasumi Atsushi, A. Suzuki +9 more

   200964 citations

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4. A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

   K. Kushida, A. Suzuki, G. Fukano, A. Kawasumi +6 more

   2009IEEE Journal of Solid-State Circuits48 citations

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5. A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS

   Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, A. Suzuki +7 more

   201047 citations

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6. A low leakage SRAM macro with replica cell biasing scheme

   Y. Takeyama, Hiroyuki Otake, O. Hirabayashi, K. Kushida +1 more

   2006Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.47 citations

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7. A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

   A. Kawasumi, T. Yabe, Y. Takeyama, O. Hirabayashi +7 more

   2008IEEE International Solid-State Circuits Conference42 citations

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8. A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers

   Yusuke Niki, A. Kawasumi, A. Suzuki, Y. Takeyama +5 more

   20102010 IEEE Asian Solid-State Circuits Conference37 citations

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9. A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS

   Yuki Fujimura, O. Hirabayashi, Takahiko Sasaki, A. Suzuki +7 more

   2010IEEE International Solid-State Circuits Conference36 citations

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10. A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme

    K. Kushida, A. Suzuki, Gou Fukano, A. Kawasumi +6 more

    20082008 IEEE Symposium on VLSI Circuits31 citations

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11. 13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current

    T. Fukuda, Koji Kohara, T. Dozaka, Y. Takeyama +5 more

    2014IEEE International Solid-State Circuits Conference22 citations

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12. A 65nm 1Mb SRAM Macro with Dynamic Voltage Scaling in Dual Power Supply Scheme for Low Power SoCs

    G. Fukano, K. Kushida, A. Tohata, Y. Takeyama +4 more

    20082008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design22 citations

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13. A 7ns-Access-Time 25μW/MHz 128kb SRAM for Low-Power Fast Wake-Up MCU in 65nm CMOS with 27fA/b Retention Current

    T. Fukuda, Kohara Koji, Dozaka Toshiaki, Y. Takeyama +5 more

    201414 citations

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14. A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

    F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno +7 more

    2013IEEE Journal of Solid-State Circuits12 citations

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15. A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs

    A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida +4 more

    2012Symposium on VLSI Circuits12 citations

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16. A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

    Yusuke Niki, Kawasumi Atsushi, A. Suzuki, Y. Takeyama +5 more

    201110 citations

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17. A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers

    A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida +2 more

    2009IEEE Journal of Solid-State Circuits10 citations

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18. A low supply voltage operation SRAM with HCI trimmed sense amplifiers

    A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida +2 more

    20092009 IEEE Asian Solid-State Circuits Conference7 citations

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19. A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

    F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno +7 more

    20132013 IEEE International Solid-State Circuits Conference Digest of Technical Papers6 citations

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20. Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction

    A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida +4 more

    20122012 IEEE International Conference on IC Design & Technology6 citations

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21. DFT techniques for wafer-level at-speed testing of high-speed SRAMs

    O. Hirabayashi, A. Suzuki, T. Yabe, A. Kawasumi +4 more

    2002Proceedings. International Test Conference5 citations

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22. A trimless, 0.5V–1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access

    K. Kushida, O. Hirabayashi, F. Tachibana, H. Hara +8 more

    2011IEEE Asian Solid-State Circuits Conference 20114 citations

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23. A 1.8 V 18 Mb DDR CMOS SRAM with power reduction techniques

    A. Kawasumi, A. Suzuki, H. Hatada, Y. Takeyama +4 more

    20002000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)4 citations

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24. Bus architecture for 600-MHz 4.5-Mb DDR SRAM

    A. Kawasumi, A. Suzuki, H. Hatada, T. Kobayashi +4 more

    19981998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)4 citations

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25. A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell

    Takahiko Sasaki, Kawasumi Atsushi, T. Yabe, Y. Takeyama +7 more

    20083 citations

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26. Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation

    A. Katayama, T. Yabe, O. Hirabayashi, Y. Takeyama +3 more

    20082008 IEEE International Test Conference3 citations

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27. A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

    Kushida Keiichi, F. Tachibana, Osamu Hirabayashi, Y. Takeyama +7 more

    20142 citations

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28. Circuit techniques to improve disturb and write margin degraded by MOSFET variability in high-density SRAM cells

    T. Yabe, A. Kawasumi, Osamu Hirabayashi, K. Kushida +7 more

    2011Symposium on VLSI Technology1 citations

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29. A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs

    Kawasumi Atsushi, Y. Takeyama, Osamu Hirabayashi, Kushida Keiichi +4 more

    20130 citations

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30. A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit

    K. Kushida, F. Tachibana, O. Hirabayashi, Y. Takeyama +7 more

    2013International Symposium on Security in Computing and Communications0 citations

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31. A Power-Reduction Scheme for Dual-Power-Supply SRAM Using BL Power Calculator and Digital LDO

    Shizuno Miyako, F. Tachibana, Osamu Hirabayashi, Y. Takeyama +7 more

    20130 citations

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32. A low leakage SRAM macro with replica cell biasing scheme

    Y. Takeyama, Hiroyuki Otake, Osamu Hirabayashi, K. Kushida +1 more

    2005IEEE Journal of Solid-State Circuits0 citations

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33. DFT Technique for Memory Macro with Built-in ECC

    Kushida Keiichi, N. Otsuka, Osamu Hirabayashi, Y. Takeyama

    20050 citations

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34. A Low Leakage SRAM Macro with Replica Cell Biasing Scheme

    Osamu Hirabayashi, Y. Takeyama, Hiroyuki Otake, Kushida Keiichi +1 more

    20050 citations

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