F. Julien

Most-cited papers

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications
Y. Joly, L. Lopez, J. Portal, H. Aziza +3 more
2010IEEE International Conference on Solid-State and Integrated Circuit Technology25 citations
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Gate Voltage Matching Investigation for Low-Power Analog Applications
Y. Joly, L. Lopez, Laurent Truphemus, J. Portal +6 more
2013IEEE Transactions on Electron Devices13 citations
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Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress
Y. Joly, L. Lopez, J. Portal, H. Aziza +4 more
2011Microelectronics and reliability13 citations
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Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology
J. Innocenti, L. Welter, F. Julien, L. Lopez +8 more
2014Midwest Symposium on Circuits and Systems8 citations
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Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology
P. Devoge, H. Aziza, P. Lorenzini, F. Julien +8 more
2021Microelectronics and reliability7 citations Open access
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Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology
P. Devoge, H. Aziza, P. Lorenzini, F. Julien +7 more
2021International Conference on Design & Technology of Integrated Systems in Nanoscale Era5 citations Open access
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Active “multi-fingers”: Test structure to improve MOSFET matching in sub-threshold area
Y. Joly, L. Lopez, J. Portal, H. Aziza +3 more
20122012 IEEE International Conference on Microelectronic Test Structures5 citations
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Octagonal MOSFET: Reliable device for low power analog applications
Y. Joly, L. Lopez, J. Portal, H. Aziza +5 more
2011European Solid-State Device Research Conference5 citations
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Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor
P. Devoge, H. Aziza, P. Lorenzini, A. Malherbe +4 more
2022International Symposium on Circuits and Systems3 citations
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High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process
Dann Morillon, F. Julien, J. Coignus, A. Toffoli +5 more
2017International Conference on Microelectronic Test Structures3 citations
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Layout optimizations to decrease internal power and area in digital CMOS standard cells
J. Innocenti, F. Julien, J. Portal, L. Lopez +5 more
2015International Convention on Information and Communication Technology, Electronics and Microelectronics3 citations
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Study of gate contact over active area
M. Carmona, Q. Hubert, L. Lopez, F. Julien +3 more
2014Symposium on Microelectronics Technology and Devices3 citations
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Threshold voltage asymmetric degradation on octagonal MOSFET during HCI stress
Y. Joly, L. Lopez, J. Portal, H. Aziza +5 more
20123 citations
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Device and circuit-level evaluation of a zero-cost transistor architecture developed via process optimization
P. Devoge, H. Aziza, P. Lorenzini, P. Masson +5 more
2022Solid-State Electronics2 citations Open access
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Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation
P. Devoge, H. Aziza, P. Lorenzini, P. Masson +7 more
2022International Integrated Reliability Workshop2 citations
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Study of HTO-based alternative gate oxides for high voltage transistors on advanced eNVM technology
Dann Morillon, C. Pribat, F. Julien, N. Cherault +10 more
2017International Integrated Reliability Workshop2 citations
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Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area
Y. Joly, L. Truphemus, L. Lopez, J. Portal +3 more
2011International Symposium on Circuits and Systems2 citations
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Advanced 200-mm RF SOI Technology exhibiting $78\ \text{fs}\ \mathrm{R}_{\text{ON}}\times \mathrm{C}_{\text{OFF}}$ and 3.7 V breakdown voltage targeting sub 6 GHz 5G FEM
F. Gianesello, A. Fleury, F. Julien, J. Durá +19 more
2022Radio Frequency Integrated Circuits Symposium1 citations
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A Schmitt trigger to benchmark the performance of a new zero-cost transistor
P. Devoge, H. Aziza, P. Lorenzini, P. Masson +5 more
2022International Conference on Electronics, Circuits, and Systems1 citations
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Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array
T. Kempf, M. Mantelli, F. Maugain, A. Régnier +7 more
2017International Integrated Reliability Workshop1 citations Open access
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Dynamic current reduction of CMOS digital circuits through design and process optimization
J. Innocenti, L. Welter, N. Borrel, F. Julien +7 more
2015International Workshop on Power and Timing Modeling, Optimization and Simulation1 citations
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Poly-Silicon gate pre-doping implantation impact on MOSFET matching performances
Y. Joly, J. Delalleau, L. Lopez, J. Portal +4 more
2011International Conference on Design & Technology of Integrated Systems in Nanoscale Era1 citations
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How Can the Carrier Mobility in Planar Si-Based MOSFETs Be Enhanced?
Smahane Dahbi, Romain Kubica, P. Masson, J. Dura +2 more
2026Microelectronics Journal0 citations Open access
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Effective mobility in N-MOSFET: comparison of McLarty and split C–V methods, and the mobility degradation factors effects
P. Masson, Romain Kubica, Smahane Dahbi, Robin Bousmaha--Jouve +4 more
2026Semiconductor Science and Technology0 citations Open access
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Sub-60 fs RFSOI Switch Performances in Advanced 200 mm 130/65 nm Hybrid Technology
Robin Bousmaha--Jouve, J. Dura, J. Amouroux, P. Masson +10 more
2026Radio Frequency Integrated Circuits Symposium0 citations
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Embedded Characterization of MOS Gate-to-Substrate Capacitances Using Ring Oscillators
P. Devoge, Noemie Couzi, Hassen Aziza, Alexandre Malherbe +4 more
2025International Congress of Mathematicans0 citations Open access
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MOSFET electron mobility enhancement using source/drain recess
L. Antunes, P. Devoge, P. Masson, J. Amouroux +3 more
20242024 IEEE International Conference on Design, Test and Technology of Integrated Systems (DTTIS)0 citations
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Performance Trade-Off of RFSOI Switches Under Scaled Bias Conditions
Siddharth Dhar, S. Monfray, F. Gianesello, F. Julien +19 more
20232023 IEEE 23rd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems0 citations
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Gate oxide degradation assessment by electrical stress and capacitance measurements
Dann Morillon, P. Masson, F. Julien, P. Lorenzini +9 more
2018International Integrated Reliability Workshop0 citations
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