G. Hiblot

Most-cited papers

Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed with Back-side Power Delivery Network
R. Chen, M. Lofrano, G. Mirabelli, G. Sisto +11 more
2022International Electron Devices Meeting33 citations
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Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster
A. Veloso, A. Jourdain, G. Hiblot, F. Schleicher +26 more
2021Symposium on VLSI Technology28 citations
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CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark
Hsiao-Hsuan Liu, P. Schuddinck, Zhenlin Pei, L. Verschueren +12 more
2023IEEE Transactions on Electron Devices25 citations
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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
A. Veloso, A. Jourdain, D. Radisic, R. Chen +40 more
2022IEEE Transactions on Electron Devices25 citations
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Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals
G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo
2015IEEE Transactions on Electron Devices25 citations
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Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node
R. Chen, G. Sisto, A. Jourdain, G. Hiblot +12 more
2021International Electron Devices Meeting22 citations Open access
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Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing
A. Beckers, J. Michl, A. Grill, B. Kaczer +6 more
2022IEEE transactions on nanotechnology19 citations Open access
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Controlled domain wall pinning in nanowires with perpendicular magnetic anisotropy by localized fringing fields
S. Breitkreutz, I. Eichwald, J. Kiermaier, G. Hiblot +4 more
201418 citations
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Ultimate MRAM Scaling: Design Exploration of High-Density, High-Performance and Energy-Efficient VGSOT for Last Level Cache
M. Gupta, Y. Xiangt, F. García-Redondo, K. Cai +7 more
2023International Electron Devices Meeting17 citations
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Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices
G. Hiblot, S. Van Huylenbroeck, G. van der Plas, B. De Wachter +7 more
2018IEEE Electron Devices Technology and Manufacturing Conference13 citations
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Accurate Boundary Condition for Short-Channel Effect Compact Modeling in MOS Devices
G. Hiblot, Tapas Dutta, Q. Rafhay, J. Lacord +3 more
2015IEEE Transactions on Electron Devices13 citations
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Analytical relationship between subthreshold swing of thermionic and tunnelling currents
G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo
201413 citations Open access
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Analytical Model for the Inversion Gate Capacitance of DG and UTBB MOSFETs at the Quantum Capacitance Limit
G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo
2015IEEE Transactions on Electron Devices12 citations
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Electrical Characterization of BEOL Plasma-Induced Damage in Bulk FinFET Technology
G. Hiblot, A. Subirats, Ye-Fan Liu, G. van der Plas
2019IEEE transactions on device and materials reliability11 citations
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DIBL–Compensated Extraction of the Channel Length Modulation Coefficient in MOSFETs
G. Hiblot
2018IEEE Transactions on Electron Devices11 citations
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Impacts of Through-Silicon Vias on Total-Ionizing-Dose Effects and Low-Frequency Noise in FinFETs
Kan Li, En Zhang, M. Gorchichko, Peng-Fei Wang +9 more
2021IEEE Transactions on Nuclear Science10 citations
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Stacked-Nanowire and FinFET Transistors: Guidelines for the 7nm Node
Loïc Gaben, S. Barraud, M. Jaud, S. Martinie +8 more
20159 citations
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Silicon-contacted waveguide integrated Ge/Si avalanche photodiode with 32 GHz bandwidth and multiplication gain >8
S. A. Srinivasan, P. De Heyn, G. Hiblot, Hongtao Chen +3 more
2019European Conference on Optical Communication8 citations
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Factor Analysis of Plasma-Induced Damage in Bulk FinFET Technology
G. Hiblot, G. van der Plas
2018IEEE Electron Device Letters8 citations
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Investigation of the Impact of Externally Applied Out-of-Plane Stress on Ferroelectric FET
Ye-Fan Liu, S. Clima, G. Hiblot, P. Matagne +4 more
2021IEEE Electron Device Letters7 citations
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Observation of Plasma-Induced Damage in Bulk Germanium ${p}$ -Type FinFET Devices and Curing in High-Pressure Anneal
G. Hiblot, H. Arimura, L. Witters, E. Chiu +5 more
2019IEEE transactions on device and materials reliability7 citations
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Impact of short-channel effects on velocity overshoot in MOSFET
G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo
2015IEEE International New Circuits and Systems Conference7 citations
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In-situ Investigation of the Impact of Externally Applied Vertical Stress on III-V Bipolar Transistor
Ye-Fan Liu, G. Hiblot, M. Gonzalez, K. Vanstreels +4 more
2018International Electron Devices Meeting6 citations
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CMOS roadmap analysis from the perspective of III-V technology using MASTAR
G. Hiblot, Q. Rafhay, G. Mugny, G. Ghibaudo +1 more
2015IEEE Silicon Nanoelectronics Workshop6 citations
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Low-Capacitance, High-Speed O-band GeSi Quantum-Confined Stark Effect Electro Absorption Modulator
A. Kandeel, G. Hiblot, C. Porret, S. A. Srinivasan +9 more
2022Frontiers in Optics + Laser Science 2022 (FIO, LS)5 citations
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Impact of Sub-µm Wafer Thinning on Latch-up Risk in STCO Scaling Era
K. Serbulova, Shih-Hung Chen, G. Hellings, G. Hiblot +5 more
2021Electrical Overstress/Electrostatic Discharge Symposium5 citations
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Towards nonvolatile magnetic crossbar arrays: A three-dimensional-integrated field-coupled domain wall gate with perpendicular anisotropy
S. Breitkreutz, I. Eichwald, G. Ziemys, G. Hiblot +3 more
20155 citations
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Impact of quantum modulation of the inversion charge in the MOSFET subthreshold regime
G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo
2014European Solid-State Device Research Conference5 citations
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Increasing Functionality of Wafer’s Backside: Analysis of Si and WS₂ Backside Power-Switch
G. Mirabelli, R. Chen, Z. Ahmed, B. Chehab +5 more
2023IEEE Transactions on Electron Devices4 citations
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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
A. Veloso, A. Jourdain, D. Radisic, Rongmei Chen +40 more
20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)4 citations
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Process-induced charging damage in IGZO nTFTs
G. Hiblot, N. Rassoul, L. Teugels, K. Devriendt +5 more
2021IEEE International Reliability Physics Symposium4 citations
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Compact Model for Inversion Charge in III–V Bulk MOSFET Including Non-Parabolicity
G. Hiblot, G. Mugny, Q. Rafhay, F. Boeuf +1 more
2015IEEE transactions on nanotechnology4 citations
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Backside Power Delivery with a Direct 14:1/19:1 High-Ratio Point-of-Load Power Converter for Servers and Datacenters
H. Lin, G. Hiblot, X. Sun, G. Talmelli +7 more
2021Symposium on VLSI Technology3 citations
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Study of out-of-plane mechanical stress impact on Si BJT and diffusion resistor using in-situ nanoindentation probing
Ye-Fan Liu, G. Hiblot, T. Furuhashi, Hesheng Lin +2 more
2019Microelectronics and reliability3 citations
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Bulk FinFET EOT Extraction from Accumulation Capacitance Measurements
G. Hiblot
2018IEEE Transactions on Electron Devices3 citations
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New Charge Pumping Current Model Assuming Exponential Tails in the Trap Energy Distribution
G. Hiblot
2018IEEE Electron Device Letters3 citations
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Full-Loop Equivalent Circuit Model for Plasma-Induced Damage Simulation
G. Hiblot, G. van der Plas
2018IEEE Transactions on Plasma Science3 citations
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Design-Technology Co-Optimization for Future CMOS:from finFET to CFETs and Backside Power
G. Hellings, P. Schuddinck, Samantha Liu, S. Salahuddin +7 more
2022Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials2 citations
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Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage
G. Hiblot, Ye-Fan Liu, G. Hellings, G. van der Plas
2019IEEE International Reliability Physics Symposium2 citations
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Impact of Local-Interconnect to Gate Overlay on Series Resistance Compensation for Injection Velocity Extraction
G. Hiblot
2018IEEE transactions on semiconductor manufacturing2 citations
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Towards nonvolatile magnetic crossbar arrays: a 3D-integrated field-coupled domain wall gate with perpendicular anisotropy
S. Breitkreutz, I. Eichwald, Ziemys Grazvydas, G. Hiblot +3 more
20152 citations
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Compact modeling of subthreshold swing in double gate and nanowire MOSFETs, for Si and GaAs channel materials
G. Hiblot, Q. Rafhay, F. Boeuf, G. Ghibaudo
20152 citations
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Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR
G. Hiblot, Q. Rafhay, L. Gaben, G. Ghibaudo +1 more
2015European Solid-State Device Research Conference2 citations
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NPN SiGe Hetero Junction Transistor Latch-Up Memory Selector
G. Hiblot, T. Ravsher, R. Loo, B. Y. V. Ramana +9 more
2023IEEE Electron Device Letters1 citations Open access
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NPN Si/SiGe memory selector with non-linearity>105 and ON-current>6MA/cm2
G. Hiblot, T. Ravsher, R. Loo, B. Y. V. Ramana +8 more
2023European Solid-State Device Research Conference1 citations
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TCAD study of latch-up sensitivity to wafer thinning below 500 nm
G. Hiblot, K. Serbulova, G. Hellings, Shih-Hung Chen
2021International Semiconductor Conference1 citations
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Plasma Charging Damage in HK-First and HK-Last RMG NMOS Devices
G. Hiblot, N. Parihar, E. Dupuy, G. Mannaert +6 more
2021IEEE transactions on device and materials reliability1 citations
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Cumulated charging mechanisms at gate processing in high-κ first planar NMOS devices
G. Hiblot, N. Parihar, E. Dupuy, G. Mannaert +4 more
2020International Integrated Reliability Workshop1 citations
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Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending
Ye-Fan Liu, Hao Yu, G. Hiblot, Anastasiia Kruv +4 more
2019IEEE International Reliability Physics Symposium1 citations
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Impact of packaging stress on thinned 6T SRAM die
G. Hiblot, Ye-Fan Liu, G. van der Plas
2018International Journal of Electronics Letters1 citations
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