A. Jourdain

Most-cited papers

3D stacked IC demonstration using a through Silicon Via First approach
J. Van Olmen, A. Mercha, G. Katti, C. Huyghebaert +26 more
20082008 IEEE International Electron Devices Meeting152 citations
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3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding
G. Katti, A. Mercha, J. Van Olmen, C. Huyghebaert +11 more
2009International Electron Devices Meeting72 citations
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Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery
J. Ryckaert, Anshul Gupta, A. Jourdain, B. Chava +3 more
2019IEEE Electron Devices Technology and Manufacturing Conference49 citations
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Backside Power Delivery: Game Changer and Key Enabler of Advanced Logic Scaling and New STCO Opportunities
A. Veloso, B. Vermeersch, R. Chen, P. Matagne +14 more
2023International Electron Devices Meeting36 citations
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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
A. Veloso, A. Jourdain, D. Radisic, R. Chen +40 more
2022IEEE Transactions on Electron Devices25 citations
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High density 20μm pitch CuSn microbump process for high-end 3D applications
J. De Vos, A. Jourdain, Mehmet Akif Erismis, Wenqi Zhang +4 more
2011Electronic Components and Technology Conference23 citations
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3D stacking using Cu-Cu direct bonding
Y.-H. Hu, C.-S. Liu, M. Lii, K. Rebibis +5 more
2012IEEE International Conference on 3D System Integration12 citations
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Backside Power Delivery With Relaxed Overlay for Backside Patterning Using Extreme Wafer Thinning and Molybdenum-Filled Slit Nano Through Silicon Vias
P. Zhao, L. Witters, A. Jourdain, M. Stucchi +16 more
2024IEEE Transactions on Electron Devices10 citations
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Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias
P. Zhao, L. Witters, A. Jourdain, M. Stucchi +16 more
20242024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)10 citations
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TSV metrology and inspection challenges
R. Alapati, Y. Travaly, J. Van Olmen, R. C. Teixeira +12 more
2009IEEE International Conference on 3D System Integration10 citations
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2 μm Pitch Direct Die-to-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning and Die Singulation
Ye Lin, P. Bex, S. Suhard, Boyao Zhang +8 more
2025Electronic Components and Technology Conference9 citations
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Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
A. Veloso, A. Jourdain, D. Radisic, Rongmei Chen +40 more
20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)4 citations
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Optimizing Direct Die-to-Wafer Hybrid Bonding: The Role of Scanner Precorrection in Achieving fine Overlay Performance
A. Hsu, I. Jadli, S. Suhard, A. Jourdain +5 more
2025International Interconnect Technology Conference3 citations
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Bonding induced distortion in wafer-to-wafer bonding applications: how the scanner and Yieldstar can enable 3D integration
V. B. Blanco Carballo, V. Renaud, S. Iacovo, A. Jourdain +4 more
2024International Interconnect Technology Conference1 citations
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Laser joining of glass to silicon using adhesive for MEMS packaging applications
F. Bardin, S. Kloss, Changhai Wang, A. Moore +3 more
2006SPIE LASE1 citations
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Nano-TSV to BPR connection optimization
Assawer Soussou, M. Stucchi, A. Jourdain
2026Advanced Lithography0 citations
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Processing and cold testing of superconducting and thermal conducting TSVs
Qian Yang, Jaber Derakhshandeh, A. Dangol, A. M. Vadiraj +5 more
2026Electronic Components and Technology Conference0 citations
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Enabling Scalable Die-to-Wafer Hybrid Bonding Through Die Distortion Correction and Grid Measurement
A. Hsu, I. Jadli, A. Jourdain, S. Suhard +6 more
2026Electronic Components and Technology Conference0 citations
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Impact of Sub-μm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era
K. Serbulova, Shih-Hung Chen, G. Hellings, A. Veloso +3 more
2024IEEE Transactions on Electron Devices0 citations
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Diffraction-Based Alignment Sensor and Mark Design Optimization to Enable Fine Overlay Accuracy for 50um-Thick Si Wafer Bonded to Glass Wafer in Die-to-Wafer Bonding Applications
A. Tamaddon, I. Jadli, S. Suhard, A. Jourdain +7 more
2024Electronic Packaging Technology Conference0 citations
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Impact of Backside Power Delivery Network with Buried Power Rails on Latch-up Immunity in DTCO/STCO
K. Serbulova, S.-H. Chen, G. Hellings, A. Veloso +5 more
2023Electrical Overstress/Electrostatic Discharge Symposium0 citations
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