D. Sorin

Most-cited papers

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
Milo M. K. Martin, D. Sorin, Bradford M. Beckmann, Michael R. Marty +5 more
2005CARN1,668 citations Open access
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A Primer on Memory Consistency and Cache Coherence
D. Sorin, Mark D. Hill, David A. Wood
2012Synthesis Lectures on Computer Architecture379 citations Open access
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Why on-chip cache coherence is here to stay
Milo M. K. Martin, M. Hill, D. Sorin
2012Communications of the ACM296 citations Open access
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Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
Albert Meixner, Michael E. Bauer, D. Sorin
2007Micro256 citations
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A Primer on Memory Consistency and Cache Coherence, Second Edition
Vijay Nagarajan, D. Sorin, M. Hill, D. Wood
2020A Primer on Memory Consistency and Cache Coherence176 citations Open access
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Architectures for online error detection and recovery in multicore processors
D. Gizopoulos, Mihalis Psarakis, S. Adve, Pradeep Ramachandran +5 more
2011Design, Automation and Test in Europe137 citations
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Robot Motion Planning on a Chip
S. Murray, Will Floyd-Jones, Y. Qi, D. Sorin +1 more
2016Robotics: Science and Systems Conference130 citations Open access
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Fault Tolerant Computer Architecture
D. Sorin
2009Fault Tolerant Computer Architecture116 citations
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Coset coding to extend the lifetime of memory
Adam N. Jacobvitz, R. Calderbank, D. Sorin
2013International Symposium on High-Performance Computer Architecture113 citations
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The microarchitecture of a real-time robot motion planning accelerator
S. Murray, Will Floyd-Jones, Y. Qi, G. Konidaris +1 more
2016Micro101 citations
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Core Cannibalization Architecture: Improving lifetime chip performance for multicore processors in the presence of hard faults
Bogdan F. Romanescu, D. Sorin
2008International Conference on Parallel Architectures and Compilation Techniques99 citations
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Dynamic power gating with quality guarantees
Anita Lungu, P. Bose, A. Buyuktosunoglu, D. Sorin
2009International Symposium on Low Power Electronics and Design87 citations
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The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling
Fred A. Bower, D. Sorin, Landon P. Cox
2008IEEE Micro78 citations
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Detouring: Translating software to circumvent hard faults in simple cores
Albert Meixner, D. Sorin
2008Dependable Systems and Networks68 citations
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Fractal Coherence: Scalably Verifiable Cache Coherence
Meng Zhang, A. Lebeck, D. Sorin
2010Micro67 citations
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UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all
Bogdan F. Romanescu, A. Lebeck, D. Sorin, A. Bracy
2010International Symposium on High-Performance Computer Architecture63 citations Open access
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Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache
Nathan Sadler, D. Sorin
2006ICCD61 citations
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Error Detection Using Dynamic Dataflow Verification
Albert Meixner, D. Sorin
2007International Conference on Parallel Architectures and Compilation Techniques47 citations Open access
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Exploring memory consistency for massively-threaded throughput-oriented processors
Blake A. Hechtman, D. Sorin
2013International Symposium on Computer Architecture44 citations
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NANA
J. Patwardhan, C. Dwyer, A. Lebeck, D. Sorin
2006ACM Journal on Emerging Technologies in Computing Systems43 citations
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Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
Albert Meixner, Michael E. Bauer, D. Sorin
2008IEEE Micro39 citations
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Spin detection hardware for improved management of multithreaded systems
Tong Li, A. Lebeck, D. Sorin
2006IEEE Transactions on Parallel and Distributed Systems39 citations
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Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
Albert Meixner, D. Sorin
2009IEEE Transactions on Dependable and Secure Computing38 citations
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Multicore power management: Ensuring robustness via early-stage formal verification
Anita Lungu, P. Bose, D. Sorin, S. German +1 more
20092009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design37 citations
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A Programmable Architecture for Robot Motion Planning Acceleration
S. Murray, Will Floyd-Jones, G. Konidaris, D. Sorin
2019IEEE International Conference on Application-Specific Systems, Architectures, and Processors35 citations
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Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures
Albert Meixner, D. Sorin
20072007 IEEE 13th International Symposium on High Performance Computer Architecture34 citations
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PVCoherence: Designing flat coherence protocols for scalable verification
Meng Zhang, Jesse D. Bingham, John Erickson, D. Sorin
2014International Symposium on High-Performance Computer Architecture32 citations
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Online diagnosis of hard faults in microprocessors
Fred A. Bower, D. Sorin, Sule Ozev
2007TACO30 citations Open access
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Specifying and dynamically verifying address translation-aware memory consistency
Bogdan F. Romanescu, A. Lebeck, D. Sorin
2010ASPLOS XV28 citations Open access
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Argus: Low-Cost, Comprehensive Error Detection in Simple Cores
Albert Meixner, Michael E. Bauer, D. Sorin
2008IEEE Micro28 citations
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Circuit-level modeling for concurrent testing of operational defects due to gate oxide breakdown
J. Carter, Sule Ozev, D. Sorin
2005Design, Automation and Test in Europe27 citations Open access
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Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures
Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, D. Sorin +2 more
2021IEEE International Symposium on Performance Analysis of Systems and Software25 citations
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Correcting Two Deletions and Insertions in Racetrack Memory
Alireza Vahid, Georgios Mappouras, D. Sorin, A. Calderbank
2017arXiv.org23 citations
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Lazy Error Detection for Microprocessor Functional Units
Mahmut Yilmaz, Albert Meixner, Sule Ozev, D. Sorin
2007IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems23 citations
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GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors
Georgios Mappouras, Alireza Vahid, R. Calderbank, D. Sorin
2019Dependable Systems and Networks22 citations
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ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications
Nicolai Oswald, V. Nagarajan, D. Sorin
2018International Symposium on Computer Architecture22 citations Open access
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Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier
Mahmut Yilmaz, Derek Hower, Sule Ozev, D. Sorin
20062006 IEEE International Test Conference21 citations Open access
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Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory
Samantha Archer, Georgios Mappouras, R. Calderbank, D. Sorin
2020Dependable Systems and Networks20 citations
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Bayesian Optimization for Efficient Accelerator Synthesis
Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, D. Sorin
2020ACM Transactions on Architecture and Code Optimization (TACO)20 citations Open access
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Reduced Precision Checking for a Floating Point Adder
Patrick J. Eibl, A. D. Cook, D. Sorin
20092009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems20 citations
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Quantifying the Impact of Process Variability on Microprocessor Behavior
Bogdan F. Romanescu, Sule Ozev, D. Sorin
200619 citations
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HieraGen: Automated Generation of Concurrent, Hierarchical Cache Coherence Protocols
Nicolai Oswald, V. Nagarajan, D. Sorin
2020International Symposium on Computer Architecture18 citations Open access
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Writing cosets of a convolutional code to increase the Lifetime of Flash memory
Adam N. Jacobvitz, R. Calderbank, D. Sorin
2012Allerton Conference on Communication, Control, and Computing18 citations
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Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, D. Sorin
2008ACM International Conference on Computing Frontiers18 citations
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HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols
Nicolai Oswald, V. Nagarajan, D. Sorin, Vasilis Gavrielatos +2 more
2022International Symposium on High-Performance Computer Architecture17 citations Open access
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Multi-program benchmark definition
Adam N. Jacobvitz, Andrew D. Hilton, D. Sorin
2015IEEE International Symposium on Performance Analysis of Systems and Software16 citations Open access
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Evaluating cache coherent shared virtual memory for heterogeneous multicore chips
Blake A. Hechtman, D. Sorin
2013IEEE International Symposium on Performance Analysis of Systems and Software16 citations Open access
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Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores
Ralph Nathan, D. Sorin
2015IEEE computer architecture letters15 citations
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Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design
A. Eslami, Alfredo J. Velasco, Alireza Vahid, Georgios Mappouras +2 more
2015International Symposium on Memory Systems14 citations
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Nostradamus: Low-cost hardware-only error detection for processor cores
Ralph Nathan, D. Sorin
2014Design, Automation and Test in Europe14 citations
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