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Y. Hayashi · SciRah

Researcher profile · Semantic Scholar

Y. Hayashi

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Y. Hayashi — researcher profile on SciRah

h-index: 17
Works: 174
Citations: 1,145

Most-cited papers

A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5–20 GHz Tunable LC-VCO
A. Tanabe, K. Hijioka, H. Nagase, Y. Hayashi
2011IEEE Journal of Solid-State Circuits61 citations
Semantic Scholar
A novel BEOL transistor (BETr) with InGaZnO embedded in Cu-interconnects for on-chip high voltage I/Os in standard CMOS LSIs
Kishou Kaneko, N. Inoue, S. Saito, N. Furutake +1 more
2011Symposium on VLSI Technology43 citations
Semantic Scholar
Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations
Kishou Kaneko, N. Inoue, S. Saito, N. Furutake +4 more
2011International Electron Devices Meeting37 citations
Semantic Scholar
Chemical Structure Effects of Ring-Type Siloxane Precursors on Properties of Plasma-Polymerized Porous SiOCH Films
M. Tada, H. Yamamoto, F. Ito, T. Takeuchi +2 more
200732 citations Open access
Semantic Scholar
Improving Reliability of Copper Dual-Damascene Interconnects by Impurity Doping and Interface Strengthening
M. Tada, M. Abe, Naoya Furutake, F. Ito +3 more
2007IEEE Transactions on Electron Devices29 citations
Semantic Scholar
Performance Modeling of Low-$k$/Cu Interconnects for 32-nm-Node and Beyond
M. Tada, N. Inoue, Y. Hayashi
2009IEEE Transactions on Electron Devices26 citations
Semantic Scholar
High-voltage complementary BEOL-FETs on Cu interconnects using N-type IGZO and P-type SnO dual oxide semiconductor channels
H. Sunamura, Kishou Kaneko, N. Furutake, S. Saito +3 more
2013Symposium on VLSI Technology19 citations
Semantic Scholar
Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices
Y. Hayashi, Hiroto Ohtake, J. Kawahara, M. Tada +9 more
2008IEEE transactions on semiconductor manufacturing19 citations
Semantic Scholar
A low-power, small area quadrature LC-VCO using miniature 3D solenoid shaped inductor
A. Tanabe, K. Hijioka, H. Nagase, Y. Hayashi
20092009 IEEE Radio Frequency Integrated Circuits Symposium18 citations
Semantic Scholar
Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-k SiOCH Films with Various Hydrocarbon Content
N. Inoue, N. Furutake, F. Ito, H. Yamamoto +2 more
200818 citations
Semantic Scholar
Operation of functional circuit elements using BEOL-transistor with InGaZnO channel for on-chip high/low voltage bridging I/Os and high-current switches
Kishou Kaneko, Hiroshi Sunamura, M. Narihiro, S. Saito +3 more
2012Symposium on VLSI Technology14 citations
Semantic Scholar
Crosstalk Analysis Method of 3-D Solenoid On-chip Inductors for High-speed CMOS SoCs
Kenichiro Hijioka, A. Tanabe, Yasushi Amamiya, Y. Hayashi
2008International Interconnect Technology Conference13 citations
Semantic Scholar
Highly-Reliable Low-Resistance Cu Interconnects with PVD-Ru/Ti Barrier Metal toward Automotive LSIs
M. Tagami, Naoya Furutake, S. Saito, Y. Hayashi
2008International Interconnect Technology Conference13 citations
Semantic Scholar
Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films
M. Tada, Hiroto Ohtake, F. Ito, Mitsuru Narihiro +8 more
2007IEEE Transactions on Electron Devices13 citations
Semantic Scholar
Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners
M. Tada, T. Tamura, F. Ito, Hiroto Ohtake +14 more
2006IEEE Transactions on Electron Devices12 citations
Semantic Scholar
Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology
Hiroto Ohtake, Masayoshi Tagami, M. Tada, M. Ueki +4 more
2006IEEE transactions on semiconductor manufacturing11 citations
Semantic Scholar
High on/off-ratio P-type oxide-based transistors integrated onto Cu-interconnects for on-chip high/low voltage-bridging BEOL-CMOS I/Os
Hiroshi Sunamura, Kishou Kaneko, N. Furutake, S. Saito +4 more
2012International Electron Devices Meeting10 citations
Semantic Scholar
Highly-oriented PVD Ruthenium Liner for Low-resistance Direct-plated Cu Interconnects
M. Abe, M. Ueki, M. Tada, T. Onodera +4 more
20072007 IEEE International Interconnect Technology Conferencee10 citations
Semantic Scholar
Characterization of Low-k/Cu Damascene Structures Using Monoenergetic Positron Beams
A. Uedono, N. Inoue, Y. Hayashi, K. Eguchi +6 more
20099 citations Open access
Semantic Scholar
Defectless Monolithic Low-k/Cu Interconnects Produced by Chemically Controlled Chemical Mechanical Polishing Process with In situ End-Point-Detection Technique
M. Ueki, T. Onodera, A. Ishikawa, Susumu Hoshino +1 more
20098 citations
Semantic Scholar
High Performance Ultra Low-k (k=2.0/keff=2.4)/Cu Dual-Damascene Interconnect Technology with Self-Formed MnSixOy Barrier Layer for 32 nm-node
T. Usui, K. Tsumura, H. Nasu, Y. Hayashi +10 more
2006International Interconnect Technology Conference8 citations
Semantic Scholar
High-Performance Cu-Interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices
M. Tagami, Hiroto Ohtake, M. Tada, M. Ueki +19 more
20062006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.7 citations
Semantic Scholar
Stabilizing Schemes for the Minority Failure Bits in Ta2O5-Based ReRAM Macro
M. Ueki, Y. Hayashi, N. Furutake, K. Masuzaki +7 more
2017IEEE Transactions on Electron Devices6 citations
Semantic Scholar
Enhanced drivability of high-Vbd dual-oxide-based complementary BEOL-FETs for compact on-chip pre-driver applications
Hiroshi Sunamura, N. Inoue, N. Furutake, S. Saito +3 more
2014Symposium on VLSI Technology6 citations
Semantic Scholar
A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics
Kenichiro Hijioka, N. Inoue, I. Kume, J. Kawahara +13 more
2010International Electron Devices Meeting6 citations
Semantic Scholar
Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles
Y. Hayashi, Mari Abe, M. Tada, Mitsuru Narihiro +9 more
2009IEEE Transactions on Electron Devices6 citations
Semantic Scholar
45nm-node Interconnects with Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications
N. Inoue, M. Tagami, Fuminori Itoh, H. Yamamoto +7 more
20072007 IEEE International Interconnect Technology Conferencee6 citations
Semantic Scholar
Plasma Co-polymerization Technology with Molecular-level Structure Tightening in "In-situ" SiOCH Stacks for 32nm-node Cu Interconnects
M. Tada, H. Yamamoto, F. Ito, M. Narihiro +14 more
2006International Electron Devices Meeting6 citations
Semantic Scholar
High Performance High-k MIM Capacitor with Plug-in Plate (PiP) for Power Delivery Line Hige-Speed MPUs
N. Inoue, Hiroto Ohtake, I. Kume, N. Furutake +6 more
2006International Interconnect Technology Conference6 citations
Semantic Scholar
Improvement of Uniformity and Reliability of Scaled-Down Cu Interconnects with Carbon-Rich Low-k Films
I. Kume, M. Ueki, N. Inoue, J. Kawahara +4 more
20115 citations Open access
Semantic Scholar
Porous Low-k Impacts on Performance of Advanced LSI Devices with GHz Operations
M. Tada, N. Inoue, J. Kawahara, H. Yamamoto +15 more
20095 citations Open access
Semantic Scholar
High performance Cu interconnects with damage-less full molecular-pore-stack (MPS) SiOCH for 32nm-node LSIs and beyond
M. Ueki, M. Tagami, F. Ito, I. Kume +10 more
20082008 IEEE International Electron Devices Meeting5 citations
Semantic Scholar
Robust BEOL Process Integration with Ultra Low-k (k=2.0) Dielectric and Self-Formed MnOx Barrier Technology for 32 nm-node and beyond
T. Watanabe, Y. Hayashi, Hideyuki Tomizawa, T. Usui +4 more
2008International Interconnect Technology Conference5 citations
Semantic Scholar
Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors
N. Inoue, I. Kume, J. Kawahara, S. Saito +8 more
20075 citations
Semantic Scholar
A Novel Monitoring Method of RF Characteristics Variations for Sub-0.1μm MOSFETs with Precise Gate-resistance Model
A. Tanabe, K. Hijioka, Y. Hayashi
2006IEEE Custom Integrated Circuits Conference5 citations
Semantic Scholar
A 5–20GHz tunable LC-VCO using variable bridge inductor
A. Tanabe, K. Hijioka, H. Nagase, Y. Hayashi
2010Symposium on VLSI Circuits4 citations
Semantic Scholar
Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-k/Cu Interconnects
I. Kume, N. Inoue, S. Saito, N. Furutake +2 more
20104 citations
Semantic Scholar
Highly-reliable molecular-pore-stack (MPS)-SiOCH/Cu interconnects with CoWB metal-cap films
M. Tagami, Naoya Furutake, N. Inoue, E. Nakazawa +2 more
20092009 IEEE International Interconnect Technology Conference4 citations
Semantic Scholar
Microstructure Control of Low-Loss Ni–Zn Ferrite by Low-Temperature Sputtering for On-Chip Magnetic Film
Kishou Kaneko, N. Inoue, N. Furutake, K. Hijioka +1 more
20094 citations Open access
Semantic Scholar
Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film
K. Kinoshita, M. Tada, M. Hiroi, K. Shiba +6 more
2008IEEE transactions on semiconductor manufacturing4 citations
Semantic Scholar
A metallurgical prescription for electromigration (EM) reliability improvment in scaled-down, Cu dual damascene interconnects
M. Tada, M. Abe, Hiroto Ohtake, Naoya Furutake +10 more
2006International Interconnect Technology Conference4 citations
Semantic Scholar
A Robust Low-$k$/Cu Dual Damascene Interconnect (DDI) With Sidewall Protection Layer (SPL)
M. Ueki, M. Tada, Masayoshi Tagami, Mitsuru Narihiro +2 more
2011IEEE transactions on device and materials reliability3 citations
Semantic Scholar
A Novel Multilayered Ni–Zn-Ferrite/TaN Film for RF/Mobile Applications
Kishou Kaneko, N. Inoue, N. Furutake, Y. Hayashi
20103 citations Open access
Semantic Scholar
Impact of oxygen on Cu surface for highly reliable low-k/Cu interconnects with CuSiN and Ti-based barrier metal
Y. Hayashi, N. Matsunaga, M. Wada, S. Nakao +5 more
20102010 IEEE International Interconnect Technology Conference3 citations
Semantic Scholar
A low power LNA using miniature 3D inductor without area penalty of passive components
A. Tanabe, K. Hijioka, H. Nagase, Y. Hayashi
20102010 IEEE Radio Frequency Integrated Circuits Symposium3 citations
Semantic Scholar
RF performance upgrading of low-power 40nm-node CMOS devices by extremely low-resistance partially-thickened local (PTL)-interconnects
Kenichiro Hijioka, J. Kawahara, M. Narihiro, I. Kume +9 more
2009International Electron Devices Meeting3 citations
Semantic Scholar
Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond
Y. Hayashi, N. Matsunaga, M. Wada, S. Nakao +3 more
20092009 IEEE International Interconnect Technology Conference3 citations
Semantic Scholar
Plasma-Enhanced Co-Polymerization of Organo-siloxane and Hydrocarbon for Low-k/Cu Interconnects
J. Kawahara, A. Nakano, N. Kunimi, K. Kinoshita +11 more
20073 citations
Semantic Scholar
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation
N. Oda, H. Imura, Naoyoshi Kawahara, M. Tagami +8 more
2007IEICE transactions on electronics3 citations
Semantic Scholar
Cost-effective and High Performance Cu Interconnects (keff=2.75) with Continuous SiOCH Stack Incorporating a Low-k Barrier Cap (k=3.1)
M. Ueki, H. Yamamoto, F. Ito, J. Kawahara +6 more
20072007 IEEE International Electron Devices Meeting3 citations
Semantic Scholar

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N. Inoue — researcher profile on SciRah
N. Furutake×20
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M. Tada×18
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M. Tada — researcher profile on SciRah
S. Saito×17
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M. Ueki — researcher profile on SciRah

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T. Takeuchi×14

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J. Kawahara×12

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Naoya Furutake×12

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T. Onodera — researcher profile on SciRah

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A. Tanabe — researcher profile on SciRah

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M. Tagami — researcher profile on SciRah