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K. Chandrashekar · SciRah

Researcher profile · Semantic Scholar

K. Chandrashekar

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K. Chandrashekar — researcher profile on SciRah

h-index: 9
Works: 20
Citations: 338

Most-cited papers

A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS
A. Ravi, P. Madoglio, Hong-Tao Xu, K. Chandrashekar +9 more
2012IEEE Journal of Solid-State Circuits90 citations
Semantic Scholar
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications
P. Madoglio, Hong-Tao Xu, K. Chandrashekar, L. Cuellar +18 more
2017IEEE International Solid-State Circuits Conference53 citations
Semantic Scholar
A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS
P. Madoglio, A. Ravi, Hong-Tao Xu, K. Chandrashekar +8 more
2012IEEE International Solid-State Circuits Conference43 citations
Semantic Scholar
A 10 b 50 MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs
K. Chandrashekar, B. Bakkaloglu
2011IEEE Transactions on Very Large Scale Integration (VLSI) Systems25 citations
Semantic Scholar
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS
Somnath Kundu, Likai Chai, K. Chandrashekar, S. Pellerano +1 more
2021IEEE Journal of Solid-State Circuits23 citations
Semantic Scholar
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique
H. Kim, Carlos Ornelas, K. Chandrashekar, D. Shi +4 more
2013IEEE Journal of Solid-State Circuits22 citations
Semantic Scholar
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management
K. Chandrashekar, S. Pellerano, P. Madoglio, A. Ravi +1 more
2012IEEE International Solid-State Circuits Conference19 citations
Semantic Scholar
A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling
K. Chandrashekar, M. Corsi, J. Fattaruso, B. Bakkaloglu
2010IEEE Transactions on Circuits and Systems - II - Express Briefs18 citations
Semantic Scholar
25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS
Somnath Kundu, Likai Chai, K. Chandrashekar, S. Pellerano +1 more
2020IEEE International Solid-State Circuits Conference13 citations
Semantic Scholar
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS
Yu-Lin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman +11 more
2012Symposium on VLSI Circuits9 citations
Semantic Scholar
A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC
H. Kim, Carlos Ornelas, K. Chandrashekar, Pin-En Su +3 more
20122012 Proceedings of the ESSCIRC (ESSCIRC)7 citations
Semantic Scholar
A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs
K. Chandrashekar, B. Bakkaloglu
2009IEEE Custom Integrated Circuits Conference5 citations
Semantic Scholar
A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision
T. Copani, B. Vermeire, Anuj Jain, Habib Karaki +8 more
2008IEEE Custom Integrated Circuits Conference5 citations
Semantic Scholar
Design of Power, Dynamic Range, Bandwidth and Noise Scalable ADCs
B. Bakkaloglu, S. Kiaei, H. Kim, K. Chandrashekar
20143 citations
Semantic Scholar
A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology
Ragh Kuttappa, V. Honkote, Amreesh Rao, Gaurav Kamalkar +8 more
2025IEEE Solid-State Circuits Letters2 citations
Semantic Scholar
Wide bandwidth transimpedance amplifier using modified Cherry Hooper amplifier
K. Chandrashekar
20071 citations
Semantic Scholar
A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O
William Y. Li, H. Kim, K. Chandrashekar, K. M. Nguyen +1 more
2017International Symposium on Low Power Electronics and Design0 citations
Semantic Scholar
Calibration of a segmented digital-time converter
P. Madoglio, G. Palaskas, S. Pellerano, A. Ravi +1 more
20150 citations
Semantic Scholar
Power scalable and low power design techniques for pipeline ADCs
K. Chandrashekar
20100 citations
Semantic Scholar
Design of digital FIR Filter using SPST based multipliers
K. Chandrashekar
20080 citations
Semantic Scholar

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A. Ravi×9
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A. Ravi — researcher profile on SciRah
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P. Madoglio×7
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