Stéphan Jourdan

Most-cited papers

Haswell: The Fourth-Generation Intel Core Processor
Per Hammarlund, Alberto J. Martinez, Atiq Bajwa, David L. Hill +17 more
2014IEEE Micro265 citations
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A stateless, content-directed data prefetching mechanism
Robert Cooksey, Stéphan Jourdan, D. Grunwald
2002ASPLOS X191 citations
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Speculation techniques for improving load related instruction scheduling
A. Yoaz, M. Erez, R. Ronen, Stéphan Jourdan
1999Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)172 citations Open access
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Multiple-block ahead branch predictors
André Seznec, Stéphan Jourdan, P. Sainrat, P. Michaud
1996ASPLOS VII127 citations Open access
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Correlated load-address predictors
Michael Bekerman, Stéphan Jourdan, R. Ronen, G. Kirshenboim +3 more
1999Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)114 citations
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Exploring instruction-fetch bandwidth requirement in wide-issue superscalar processors
P. Michaud, André Seznec, Stéphan Jourdan
1999International Conference on Parallel Architectures and Compilation Techniques62 citations
Semantic Scholar
The effects of mispredicted-path execution on branch prediction structures
Stéphan Jourdan, T. Hsing, Jared Stark, Y. Patt
1996Proceedings of the 1996 Conference on Parallel Architectures and Compilation Technique42 citations
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An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors
P. Michaud, André Seznec, Stéphan Jourdan
2001International journal of parallel programming40 citations
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Exploring configurations of functional units in an out-of-order superscalar processor
Stéphan Jourdan, P. Sainrat, D. Litaize
1995Proceedings 22nd Annual International Symposium on Computer Architecture35 citations Open access
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eXtended block cache
Stéphan Jourdan, Lihu Rappoport, Yoav Almog, M. Erez +2 more
2000Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)20 citations
Semantic Scholar
Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution
Stéphan Jourdan, Jared Stark, T. Hsing, Y. Patt
1997International journal of parallel programming16 citations
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An investigation of the performance of various instruction-issue buffer topologies
Stéphan Jourdan, P. Sainrat, D. Litaize
1995MICRO 2812 citations
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Optimized Memory Tagging on Ampereone ® Processors
S. Kaushik, M. Madhav, Nagi Aboulenein, Jason Bessette +13 more
2025International Symposium on Computer Architecture7 citations Open access
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An investigation of the performance of various instruction-issue buffer topologies
Stéphan Jourdan, P. Sainrat, D. Litaize
1995Proceedings of the 28th Annual International Symposium on Microarchitecture4 citations
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Transitioning the Intel® next generation microarchitectures (nehalem and westmere) into the mainstream
L. P. Looi, Stéphan Jourdan
2009IEEE Hot Chips Symposium1 citations
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Alternative Schemes for High-Bandwidth Instruction Fetching
P. Michaud, André Seznec, Stéphan Jourdan, P. Sainrat
19981 citations
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A high out-of-order issue symmetric superpipeline superscalar microprocessor
Stéphan Jourdan, D. Carrière, D. Litaize
1994Proceedings of Twentieth Euromicro Conference. System Architecture and Integration1 citations
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miniature pressure sensor has metal membrane and method of manufacturing
Fabien Lemery, Stéphan Jourdan, David Cayez
20150 citations
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Throttling an integrated compound
R. Mayer, L. P. Looi, Ravi Rajwar, Stéphan Jourdan
20110 citations
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Early Load Address Resolution Through Register Tracking
Michael Bekerman, A. Yoaz, F. Gabbay, Stéphan Jourdan +2 more
19990 citations
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Increasing the Instruction-Level Parallelism through Data-Flow Manipulation
Stéphan Jourdan, A. Yoaz, M. Erez
19990 citations
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