Sae Kyu Lee

Most-cited papers

1. Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators

   Brandon Reagen, P. Whatmough, Robert Adolf, Saketh Rama +5 more

   2016International Symposium on Computer Architecture616 citations

   Semantic Scholar

   Save

2. Ares: A framework for quantifying the resilience of deep neural networks

   Brandon Reagen, Udit Gupta, Lillian Pentecost, P. Whatmough +4 more

   2018Design Automation Conference376 citations Open access

   Semantic Scholar

   Save

3. 14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications

   P. Whatmough, Sae Kyu Lee, Hyunkwang Lee, Saketh Rama +2 more

   2017IEEE International Solid-State Circuits Conference156 citations

   Semantic Scholar

   Save

4. A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

   Ankur Agrawal, Sae Kyu Lee, J. Silberman, M. Ziegler +40 more

   2021IEEE International Solid-State Circuits Conference109 citations

   Semantic Scholar

   Save

5. DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications

   P. Whatmough, Sae Kyu Lee, D. Brooks, Gu-Yeon Wei

   2018IEEE Journal of Solid-State Circuits88 citations

   Semantic Scholar

   Save

6. Characterizing and evaluating voltage noise in multi-core near-threshold processors

   Xuan Zhang, Tao Tong, Svilen Kanev, Sae Kyu Lee +2 more

   2013International Symposium on Low Power Electronics and Design39 citations

   Semantic Scholar

   Save

7. A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference

   Jinwook Oh, Sae Kyu Lee, Min-Gu Kang, M. Ziegler +39 more

   20202020 IEEE Symposium on VLSI Circuits38 citations

   Semantic Scholar

   Save

8. A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications

   Tao Tong, Sae Kyu Lee, Xuan Zhang, D. Brooks +1 more

   2016IEEE Journal of Solid-State Circuits38 citations

   Semantic Scholar

   Save

9. A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

   Sae Kyu Lee, Ankur Agrawal, J. Silberman, M. Ziegler +40 more

   2022IEEE Journal of Solid-State Circuits36 citations

   Semantic Scholar

   Save

10. A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators

    P. Whatmough, Sae Kyu Lee, Marco Donato, Hsea-Ching Hsueh +6 more

    2019Symposium on VLSI Circuits34 citations

    Semantic Scholar

    Save

11. A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter

    Sae Kyu Lee, Tao Tong, Xuan Zhang, D. Brooks +1 more

    2015Symposium on VLSI Circuits27 citations

    Semantic Scholar

    Save

12. SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators

    Sae Kyu Lee, P. Whatmough, Marco Donato, Glenn G. Ko +2 more

    2022IEEE Journal of Solid-State Circuits26 citations

    Semantic Scholar

    Save

13. Evaluation of voltage stacking for near-threshold multicore computing

    Sae Kyu Lee, D. Brooks, Gu-Yeon Wei

    2012International Symposium on Low Power Electronics and Design26 citations Open access

    Semantic Scholar

    Save

14. A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC–DC Converter

    Sae Kyu Lee, Tao Tong, Xuan Zhang, D. Brooks +1 more

    2017IEEE Transactions on Very Large Scale Integration (vlsi) Systems24 citations Open access

    Semantic Scholar

    Save

15. A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle

    Xuan Zhang, Mario Lok, Tao Tong, Sae Kyu Lee +6 more

    2017IEEE Journal of Solid-State Circuits23 citations Open access

    Semantic Scholar

    Save

16. CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development

    P. Whatmough, Marco Donato, Glenn G. Ko, Sae Kyu Lee +2 more

    2020IEEE Micro19 citations Open access

    Semantic Scholar

    Save

17. A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs

    Sae Kyu Lee, P. Whatmough, D. Brooks, Gu-Yeon Wei

    2019IEEE Journal of Solid-State Circuits19 citations Open access

    Semantic Scholar

    Save

18. A multi-chip system optimized for insect-scale flapping-wing robots

    Xuan Zhang, Mario Lok, Tao Tong, Simon Chaput +5 more

    2015Symposium on VLSI Circuits15 citations

    Semantic Scholar

    Save

19. Fully-CMOS Multi-Level Embedded Non-Volatile Memory Devices With Reliable Long-Term Retention for Efficient Storage of Neural Network Weights

    Siming Ma, Marco Donato, Sae Kyu Lee, D. Brooks +1 more

    2019IEEE Electron Device Letters8 citations

    Semantic Scholar

    Save

20. A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET

    Sae Kyu Lee, P. Whatmough, Niamh Mulholland, Patrick Hansen +2 more

    2018European Solid-State Circuits Conference4 citations

    Semantic Scholar

    Save

21. TuneLogic: Post-silicon tuning of dual-Vdd designs

    Stephen Bijansky, Sae Kyu Lee, Adnan Aziz

    2009IEEE International Symposium on Quality Electronic Design4 citations

    Semantic Scholar

    Save

22. Sub-uJ deep neural networks for embedded applications

    P. Whatmough, Sae Kyu Lee, Gu-Yeon Wei, D. Brooks

    2017Asilomar Conference on Signals, Systems and Computers1 citations

    Semantic Scholar

    Save

23. High Efficiency Power Delivery for Chip Multiprocessors Using Voltage Stacking

    Sae Kyu Lee

    20160 citations

    Semantic Scholar

    Save