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D. Lafond · SciRah

Researcher profile · Semantic Scholar

D. Lafond

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D. Lafond — researcher profile on SciRah

h-index: 25
Works: 118
Citations: 2,157

Most-cited papers

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding
O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet +15 more
20082008 IEEE International Electron Devices Meeting179 citations
Semantic Scholar
Bonded planar double-metal-gate NMOS transistors down to 10 nm
M. Vinet, T. Poiroux, Julie Widiez, J. Lolivier +13 more
2005IEEE Electron Device Letters128 citations
Semantic Scholar
Advances in 3D CMOS sequential integration
P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer +17 more
2009International Electron Devices Meeting124 citations
Semantic Scholar
Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
F. Andrieu, O. Weber, J. Mazurier, Olivier Thomas +37 more
2010Symposium on VLSI Technology101 citations
Semantic Scholar
Chemical and structural properties of conducting nanofilaments in TiN/HfO2-based resistive switching structures
P. Calka, E. Martinez, V. Delaye, D. Lafond +7 more
2013Nanotechnology84 citations Open access
Semantic Scholar
Copper Direct-Bonding Characterization and Its Interests for 3D Integration
P. Gueguen, L. Di Cioccio, P. Gergaud, M. Rivoire +6 more
200968 citations Open access
Semantic Scholar
Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack
V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet +14 more
20072007 IEEE International Electron Devices Meeting64 citations
Semantic Scholar
High density platinum nanocrystals for non-volatile memory applications
J. Dufourcq, S. Bodnar, D. Lafond, P. Mur +6 more
200857 citations
Semantic Scholar
Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack
Thomas Ernst, C. Dupre, C. Isheden, É. Bernard +19 more
2006International Electron Devices Meeting57 citations
Semantic Scholar
New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI
C. Fenouillet-Béranger, B. Mathieu, B. Previtali, M.-P. Samson +29 more
20142014 IEEE International Electron Devices Meeting52 citations
Semantic Scholar
Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX
O. Weber, F. Andrieu, J. Mazurier, M. Cassé +29 more
2010International Electron Devices Meeting48 citations
Semantic Scholar
Mechanism of Thermal Silicon Oxide Direct Wafer Bonding
C. Ventosa, C. Morales, L. Libralesso, F. Fournel +5 more
200947 citations
Semantic Scholar
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration
C. Fenouillet-Béranger, B. Previtali, P. Batude, F. Nemouchi +12 more
2014European Solid-State Device Research Conference46 citations
Semantic Scholar
GeOI and SOI 3D monolithic cell integrations for high density applications
P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer +27 more
2006Symposium on VLSI Technology45 citations
Semantic Scholar
Strain mapping at the nanoscale using precession electron diffraction in transmission electron microscope with off axis camera
Mathieu Pierre Vigouroux, V. Delaye, N. Bernier, R. Cipro +7 more
201441 citations Open access
Semantic Scholar
Degradation of floating-gate memory reliability by few electron phenomena
G. Molas, D. Deleruyelle, B. De Salvo, G. Ghibaudo +4 more
2006IEEE Transactions on Electron Devices37 citations
Semantic Scholar
3D monolithic integration
P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer +12 more
2011International Symposium on Circuits and Systems36 citations
Semantic Scholar
Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length
P. Batude, M. Vinet, C. Xu, B. Previtali +12 more
2011Symposium on VLSI Technology35 citations
Semantic Scholar
Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer
P. Morel, G. Haberfehlner, D. Lafond, G. Audoit +5 more
201233 citations
Semantic Scholar
Copper direct bonding for 3D integration
P. Gueguen, L. Di Cioccio, M. Rivoire, D. Scevola +5 more
2008International Interconnect Technology Conference33 citations
Semantic Scholar
Origin of resistivity change in NiO thin films studied by hard x-ray photoelectron spectroscopy
P. Calka, E. Martinez, D. Lafond, S. Minoret +5 more
201128 citations
Semantic Scholar
25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack
F. Andrieu, C. Dupre, F. Rochette, O. Faynot +23 more
20062006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.28 citations
Semantic Scholar
Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs down to 25nm Gate Length and Width
F. Andrieu, O. Faynot, X. Garros, D. Lafond +24 more
2006International Electron Devices Meeting28 citations
Semantic Scholar
Chemical interface analysis of as grown HfO2 ultrathin films on SiO2
C. Maunoury, K. Dabertrand, E. Martinez, M. Saadoune +7 more
200724 citations
Semantic Scholar
New insight on the charge trapping mechanisms of SiN-based memory by atomistic simulations and electrical modeling
E. Vianello, L. Perniola, Philippe Blaise, G. Molas +12 more
2009International Electron Devices Meeting22 citations Open access
Semantic Scholar
Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of ≪100≫ or ≪110≫ oriented FDSOI cMOSFETs for the 32nm Node
F. Andrieu, Olivier Faynot, F. Rochette, J. Barbe +24 more
20072007 IEEE Symposium on VLSI Technology22 citations
Semantic Scholar
Cu nanoparticles on 2D and 3D silica substrates: controlled size and density, and critical size in catalytic silicon nanowire growth
A. Roussey, P. Gentile, D. Lafond, E. Martinez +3 more
201320 citations
Semantic Scholar
Quantitative profiling of SiGe/Si superlattices by time-of-flight secondary ion mass spectrometry: the advantages of the extended Full Spectrum protocol.
M. Py, Jean-Paul Barnes, D. Lafond, J. Hartmann
2011Rapid Communications in Mass Spectrometry20 citations
Semantic Scholar
Top-Down Fabrication of Epitaxial SiGe/Si Multi-(Core/Shell) p-FET Nanowire Transistors
S. Barraud, J. Hartmann, V. Maffini-Alvaro, L. Tosti +2 more
2014IEEE Transactions on Electron Devices18 citations
Semantic Scholar
Four-dimensional spectral low-loss energy-filtered transmission electron tomography of silicon nanowire-based capacitors
Georg Haberfehlner, P. Bayle-Guillemaud, G. Audoit, D. Lafond +4 more
201218 citations
Semantic Scholar
Stability of 8-hydroxyquinoline aluminum films encapsulated by a single Al2O3 barrier deposited by low temperature atomic layer deposition
T. Maindron, Jean‐Yves Simon, Emilie Viasnoff, D. Lafond
201218 citations
Semantic Scholar
Mushroom-Free Selective Epitaxial Growth of Si, SiGe and SiGe:B Raised Sources and Drains on FD-SOI MOSFETs
J. Hartmann, V. Benevent, J. Barnes, M. Veillerot +7 more
20122012 International Silicon-Germanium Technology and Device Meeting (ISTDM)18 citations
Semantic Scholar
Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length
S. Morvan, F. Andrieu, M. Cassé, O. Weber +18 more
2012Symposium on VLSI Technology18 citations
Semantic Scholar
Co-integrated dual strained channels on fully depleted sSDOI CMOSFETs with HfO/sub 2//TiN gate stack down to 15nm gate length
F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz +14 more
20052005 IEEE International SOI Conference Proceedings18 citations
Semantic Scholar
High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator
L. Pasini, P. Batude, M. Cassé, B. Mathieu +24 more
2015Symposium on VLSI Technology17 citations
Semantic Scholar
Passivated TiN nanocrystals/SiN trapping layer for enhanced erasing in nonvolatile memory
G. Gay, D. Belhachemi, J. Colonna, S. Minoret +9 more
201017 citations
Semantic Scholar
Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment
L. Hutin, M. Vinet, T. Poiroux, C. Le Royer +10 more
2009International Electron Devices Meeting17 citations
Semantic Scholar
Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- $\kappa$ Dielectrics, and Metallic Source/Drain
M. Vinet, T. Poiroux, C. Licitra, J. Widiez +12 more
2009IEEE Electron Device Letters17 citations
Semantic Scholar
Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon–Germanium Source/Drain
S. Baudot, F. Andrieu, O. Weber, P. Perreau +8 more
2010IEEE Electron Device Letters16 citations
Semantic Scholar
Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics
J. Hartmann, F. Andrieu, D. Lafond, T. Ernst +6 more
200816 citations
Semantic Scholar
New insight on VT stability of HK/MG stacks with scaling in 30nm FDSOI technology
L. Brunet, X. Garros, M. Cassé, O. Weber +19 more
2010Symposium on VLSI Technology14 citations
Semantic Scholar
A vertical power device conductive assembly at wafer level using direct bonding technology
L. Benaissa, N. Rouger, J. Widiez, J. Crebier +4 more
2012International Symposium on Power Semiconductor Devices and IC's12 citations
Semantic Scholar
Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories
L. Masoero, G. Molas, Francesca Brun, M. Gely +18 more
2011International Electron Devices Meeting12 citations Open access
Semantic Scholar
Copper Direct Bonding Characterization and its Interests for 3D Integration Circuits
P. Gueguen, L. Di Cioccio, P. Gergaud, M. Rivoire +6 more
20089 citations Open access
Semantic Scholar
3D Vertical interconnects by Copper Direct Bonding
L. Dicioccio, P. Gueguen, P. Gergaud, M. Zussy +5 more
20089 citations
Semantic Scholar
Integration of single carbon nanofibers in standard via interconnects
J. Coiffic, D. Mariolle, N. Chevalier, S. Olivier +4 more
20089 citations
Semantic Scholar
In-depth study of strained SGOI nMOSFETs down to 30nm gate length
F. Andrieu, Thomas Ernst, O. Faynot, O. Rozeau +10 more
2005Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.9 citations
Semantic Scholar
Investigation of the role of H-related defects in Al2O3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling
G. Molas, L. Masoero, Philippe Blaise, A. Padovani +19 more
2010International Electron Devices Meeting8 citations Open access
Semantic Scholar
Manipulation of periodic Coulomb blockade oscillations in ultra-scaled memories by single electron charging of silicon nanocrystal floating gates
G. Molas, X. Jehl, Marc Sanquer, B. De Salvo +2 more
2005IEEE transactions on nanotechnology8 citations
Semantic Scholar
Study of annealing temperature influence on the performance of top gated graphene/SiC transistors
M. Clavel, T. Poiroux, M. Mouis, L. Becerra +6 more
20127 citations
Semantic Scholar

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