J. Legat

Most-cited papers

A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS
Charlotte Frenkel, M. Lefebvre, J. Legat, D. Bol
2018IEEE Transactions on Biomedical Circuits and Systems323 citations Open access
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A 0.086-mm2 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS
Charlotte Frenkel, J. Legat, D. Bol
2018arXiv.org202 citations
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Interests and Limitations of Technology Scaling for Subthreshold Logic
D. Bol, R. Ambroise, D. Flandre, J. Legat
2009IEEE Transactions on Very Large Scale Integration (vlsi) Systems171 citations
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ULPFA: A New Efficient Design of a Power-Aware Full Adder
Ilham Hassoune, D. Flandre, I. O'Connor, J. Legat
2010IEEE Transactions on Circuits and Systems Part 1: Regular Papers158 citations
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MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning
Charlotte Frenkel, J. Legat, D. Bol
2019IEEE Transactions on Biomedical Circuits and Systems155 citations Open access
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SleepWalker: A 25-MHz 0.4-V Sub- $\hbox{mm}^{2}$ 7- $\mu\hbox{W/MHz}$ Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes
D. Bol, J. De Vos, Cédric Hocquet, F. Botman +4 more
2013IEEE Journal of Solid-State Circuits112 citations
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An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications
P. Manet, D. Maufroid, L. Tosi, G. Gailliard +10 more
2008EURASIP Journal on Embedded Systems77 citations Open access
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Green SoCs for a sustainable Internet-of-Things
D. Bol, J. De Vos, F. Botman, G. de Streel +3 more
2013IEEE Faible Tension Faible Consommation62 citations
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A Flexible Hardware JPEG 2000 Decoder for Digital Cinema
Antonin Descampe, François-Olivier Devaux, G. Rouvroy, J. Legat +2 more
2006IEEE transactions on circuits and systems for video technology (Print)60 citations
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A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas
Charlotte Frenkel, J. Legat, D. Bol
2020International Symposium on Circuits and Systems51 citations Open access
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Analysis and minimization of practical energy in 45nm subthreshold logic circuits
D. Bol, R. Ambroise, D. Flandre, J. Legat
20082008 IEEE International Conference on Computer Design51 citations
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Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
D. Bol, D. Flandre, J. Legat
2009International Symposium on Low Power Electronics and Design49 citations
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Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
D. Bol, Dina Kamel, D. Flandre, J. Legat
2009International Symposium on Low Power Electronics and Design45 citations
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Harvesting the potential of nano-CMOS for lightweight cryptography: an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags
Cédric Hocquet, Dina Kamel, F. Regazzoni, J. Legat +3 more
2011Journal of Cryptographic Engineering41 citations Open access
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A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes
D. Bol, J. De Vos, Cédric Hocquet, F. Botman +4 more
2012IEEE International Solid-State Circuits Conference40 citations
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Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes
F. Botman, J. De Vos, Sebastien Bernard, François Stas +2 more
2014International Symposium on Circuits and Systems33 citations
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Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks
Ilham Hassoune, F. Macé, D. Flandre, J. Legat
2006Microelectronics Journal31 citations
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Building Ultra-Low-Power Low-Frequency Digital Circuits with High-Speed Devices
D. Bol, R. Ambroise, D. Flandre, J. Legat
20072007 14th IEEE International Conference on Electronics, Circuits and Systems29 citations
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A Design Methodology for Secured ICs Using Dynamic Current Mode Logic
F. Macé, F. Standaert, J. Quisquater, J. Legat
2005International Workshop on Power and Timing Modeling, Optimization and Simulation28 citations Open access
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Application-Specific Reconfigurable XOR-Indexing to Eliminate Cache Conflict Misses
Hans Vandierendonck, P. Manet, J. Legat
2006Proceedings of the Design Automation & Test in Europe Conference24 citations Open access
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Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks
A. K. Lusala, J. Legat
2012International Journal of Reconfigurable Computing22 citations Open access
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Combining sdm-based circuit switching with packet switching in a NoC for real-time applications
A. K. Lusala, J. Legat
2011International Symposium on Circuits and Systems21 citations
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Sub-45nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications
D. Bol, R. Ambroise, D. Flandre, J. Legat
20082008 IEEE International SOI Conference20 citations Open access
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A fully-synthesized 20-gate digital spike-based synapse with embedded online learning
Charlotte Frenkel, G. Indiveri, J. Legat, D. Bol
2017International Symposium on Circuits and Systems19 citations
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Impact of Technology Scaling on Digital Subthreshold Circuits
D. Bol, R. Ambroise, D. Flandre, J. Legat
2008IEEE Computer Society Annual Symposium on VLSI19 citations
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A 65-nm 738k-Synapse/mm2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning
Charlotte Frenkel, J. Legat, D. Bol
2019International Symposium on Circuits and Systems18 citations
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The detrimental impact of negative Celsius temperature on ultra-low-voltage CMOS logic
D. Bol, Cédric Hocquet, D. Flandre, J. Legat
2010Proceedings of ESSCIRC17 citations
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Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology
D. Bol, J. De Vos, R. Ambroise, D. Flandre +1 more
200817 citations
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A SDM-TDM based circuit-switched router for on-chip networks
A. K. Lusala, J. Legat
2011Reconfigurable Communication-centric Systems-on-Chip16 citations
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Dynamic differential self-timed logic families for robust and low-power security ICs
Ilham Hassoune, F. Macé, D. Flandre, J. Legat
2007Integr.16 citations
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A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications
A. K. Lusala, J. Legat
2012IEEE International New Circuits and Systems Conference15 citations
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NoC Implementation in FPGA using Torus Topology
A. K. Lusala, P. Manet, Bertrand Rousseau, J. Legat
2007International Conference on Field-Programmable Logic and Applications15 citations
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Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards
G. D. de Dormale, R. Ambroise, D. Bol, J. Quisquater +1 more
2006IEEE International Conference on Application-Specific Systems, Architectures, and Processors15 citations
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Practical evaluation of a radial soft hash algorithm
F. Standaert, E. Lefebvre, G. Rouvroy, B. Macq +2 more
2005International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II15 citations
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A compact phenomenological digital neuron implementing the 20 Izhikevich behaviors
Charlotte Frenkel, J. Legat, D. Bol
2017Biomedical Circuits and Systems Conference14 citations
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Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits
D. Bol, Cédric Hocquet, D. Flandre, J. Legat
2010Proceedings of 2010 IEEE International Symposium on Circuits and Systems12 citations
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A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications
Charlotte Frenkel, J. Legat, D. Bol
2015Reconfigurable Communication-centric Systems-on-Chip11 citations
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Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels
D. Bol, D. Flandre, J. Legat
2010TODE11 citations
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Combining circuit and packet switching with bus architecture in a NoC for real-time applications
A. K. Lusala, J. Legat
2010Proceedings of 2010 IEEE International Symposium on Circuits and Systems10 citations
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Enabling certification for dynamic partial reconfiguration using a minimal flow
Bertrand Rousseau, P. Manet, D. Galerin, D. Merkenbreack +3 more
20072007 Design, Automation & Test in Europe Conference & Exhibition10 citations
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MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs
Renaud Van Langendonck, A. K. Lusala, J. Legat
2012Reconfigurable Communication-centric Systems-on-Chip9 citations
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Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI
Sebastien Bernard, M. Belleville, J. Legat, A. Valentian +1 more
2016Microelectronics Journal8 citations
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A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks
A. K. Lusala, J. Legat
2010International Conference on Reconfigurable Computing and FPGAs8 citations
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Dynamically Reconfigurable Architectures for Software-Defined Radio in Professional Electronic Applications
Bertrand Rousseau, P. Manet, Thibault Delavallee, Igor Loiselle +1 more
20127 citations
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A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications
Angelo Kuti Lusala, J. Legat
2010Nordic Microelectronics Event6 citations
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Evaluation of dynamic partial reconfiguration in professional electronics applications
P. Manet, M. Di Ciano, J. Legat, R. Liberati +8 more
20076 citations
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Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
P. Manet, R. Ambroise, D. Bol, Marc Baltus +1 more
2005Journal of Low Power Electronics6 citations
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Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits
F. Botman, D. Bol, J. Legat, K. Roy
2014IEEE Transactions on Very Large Scale Integration (VLSI) Systems5 citations
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A hybrid router combining circuit switching and packet switching with bus architecture for on-chip networks
A. K. Lusala, J. Legat
2010Proceedings of the 8th IEEE International NEWCAS Conference 20105 citations
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Ultra-low-power high-noise-margin logic with undoped FD SOI devices
D. Bol, J. De Vos, D. Flandre, J. Legat
20092009 IEEE International SOI Conference5 citations
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