V. Narang

Most-cited papers

TCAD-Enabled Machine Learning Defect Prediction to Accelerate Advanced Semiconductor Device Failure Analysis
C.-W. Teo, Kain Lu Low, V. Narang, A. Thean
2019International Conference on Simulation of Semiconductor Processes and Devices42 citations
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Fault isolation in semiconductor product, process, physical and package failure analysis: Importance and overview
J. Chin, V. Narang, Xiao-Le Zhao, M. Tay +8 more
2011Microelectronics and reliability35 citations
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Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices
D. Zudhistira, V. Viswanathan, V. Narang, J.-M. Chin +3 more
201714 citations
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Physical fault isolation of complex BEOL defects in advanced microprocessors using EBAC technique in nano-prober
Lim Soon Huat, Wei Samuel, Teo Cheawei, V. Narang +4 more
2017International Symposium on the Physical and Failure Analysis of Integrated Circuits7 citations
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Electrical Characterization of FEOL Bridge Defects in Advanced Nanoscale Devices Using TCAD Simulations
C.-W. Teo, V. Narang, A. Thean
2018International Symposium on the Physical and Failure Analysis of Integrated Circuits6 citations
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Understanding Soft Defect Localization set-points for reducing cause-not-founds in integrated circuits
V. Ravikumar, S. L. Phoa, V. Narang, J.-M. Chin
2008International Symposium on the Physical and Failure Analysis of Integrated Circuits6 citations
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Integration of Probing Capability into Plasma FIB for In-Situ Delayering, Defect Inspection, and EBAC on BEOL Defects of Sub-20nm FinFET Devices
D. Zudhistira, M.-S. Wei, V. Narang, J.-M. Chin +7 more
2018ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis5 citations
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Combining High Resolution Pulsed TIVA and nanoprobing techniques to identify drive strength issues in mixed signal circuits
V. Ravikumar, M. Y. Ho, R. R. Goruganthu, S. L. Phoa +2 more
20102010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits5 citations
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Resolving systematic voltage sensitive soft failures in 28nm microprocessor devices
Dnyan Khatri, S. Lim, Mun-Yee Ho, V. Narang +2 more
2014International Symposium on the Physical and Failure Analysis of Integrated Circuits4 citations
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Thermal effect on die warpage during back-side die polishing of flip-chip BGA device
M. Monjur, M.-S. Wei, H. B. Chong, L. Nasar-Abdat +1 more
2013International Symposium on the Physical and Failure Analysis of Integrated Circuits4 citations
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Recent advances in fault isolation for semiconductor industry
J. Chin, V. Narang, M. Tay, S. L. Phoa +10 more
2013International Symposium on the Physical and Failure Analysis of Integrated Circuits4 citations
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Conductive Atomic Force Microscopy failure analysis for SOI devices
S. Lim, Xin-Hua Zheng, C.-W. Teo, V. Narang +2 more
2008International Symposium on the Physical and Failure Analysis of Integrated Circuits3 citations
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Simulation assisted uncovering and understanding of complex failures in 28nm microprocessor devices
Dnyan Khatri, V. Narang, Mun-Yee Ho, Komal Pandey +1 more
2016International Symposium on the Physical and Failure Analysis of Integrated Circuits2 citations
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Sideways FIB TEM sample preparation for improved construction analysis in TEM
H. B. Chong, B. van Leer, V. Narang, M. Y. Ho
20122012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits2 citations
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Root cause identification of subtle filament shorts in microprocessors using nano-probing
H. E. Lwin, V. Narang, J.-M. Chin
20092009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits2 citations
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In-Situ Delayering in Atomic Force Microscope for Sub-20nm Technology Devices
Matthew Yap, C.-W. Teo, V. Narang
2018International Symposium on the Physical and Failure Analysis of Integrated Circuits1 citations
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Absorbed-specimen current imaging implementation and characterization in nano-prober for resistive interconnects isolation in 45-nm silicon-on-insulator microprocessors
Ya-Liang Chen, S. Lim, V. Narang, J.-M. Chin
20102010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits1 citations
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High-temperature Conductive-AFM technique for resolution of soft failures
Lim Soon Huat, Wan-Xin Sun, V. Narang, J.-M. Chin
20092009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits1 citations
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Device-level fault isolation of advanced flip-chip devices using scanning SQUID microscopy
C.-W. Teo, H. E. Lwin, V. Narang, J.-M. Chin
2008International Symposium on the Physical and Failure Analysis of Integrated Circuits1 citations
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Evaluating High-Speed Pulsed IV Techniques for Resistive Open Via Isolation in Advanced Technology Nodes
Shang-Yi Lim, V. Narang
2026International Symposium for Testing and Failure Analysis0 citations
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International Roadmap for Failure Analysis
V. Narang
2025EDFA Technical Articles0 citations
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In-Situ Orthogonal TEM Lamella Conversion for Catching Subtle Defects in 3D Transistors of Microprocessor Devices.
D. Zudhistira, Mun-Yee Ho, V. Narang
2023Microscopy and Microanalysis0 citations Open access
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Defect Isolation Using FIB based TEM Sample Preparation Methodology for Yield and Reliability Improvement of Advanced Microprocessors
Chong Hock Bee, V. Narang
2019IEEE Electron Devices Technology and Manufacturing Conference0 citations
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Targeted Silicon Ultra-Thinning by Contour Milling for Advanced Fault Isolation
W. Teo, M.-S. Wei, V. Narang, C.-L. Gan +2 more
2019ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis0 citations
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Back-side De-processing using CMP for bulk silicon 40-nm graphics processors
M.-S. Wei, C.-W. Teo, H. B. Chong, S. H. Lim +3 more
2011International Symposium on the Physical and Failure Analysis of Integrated Circuits0 citations
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Combining Refractive Solid Immersion Lens and Pulsed Laser-Induced Technique for Integrated Circuit Failure Analysis
S.H. Goh, A. Quah, J. Phang, V. Ravikumar +4 more
2010EDFA Technical Articles0 citations
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