Simulation Methodology of DDR2 Interface with TI Processor and Timing Verification in HyperLynx

This paper discusses about the Pre-layout and Post-layout simulations methodology of DDR2 interface present between TMS3206455 (Microprocessor from Texas Instruments) and MT47H64M16 (DDR2 memory from Micron) of the controller card. Simulations have been performed in HyperLynx software. Simulation models used such as IBIS models, its validation and generated controller timing model for simulation is also discussed. Interface signals are simulated in LineSim which is Pre-layout simulation tool of HyperLynx software. Also described in this paper the constraints of signals which have been developed at the pre layout stage and ensures the proper timing of data, strobe, mask, address, control and command signals. The constraints are then exported to BoardSim which is used for Post-layout simulations. BoardSim Simulation results show the correlation with LineSim results and validate the timing between selected processor and DDR2 memory.