New Josephson-CMOS Interface Amplifier
Daniel Weia b, Stephen R. Whiteleya b, Lizhen Zhenga b, Park Heejoungc d, Hoki Kima b, T. Van Duzera b
- aDepartment of Electrical Engineering Computer Sciences, University of California, Berkeley, CA, USA
- bDept. of Electr. Eng. Comput. Sci., Univ. of Cal ifornia, Berkeley, CA, USA
- cHynix Semiconductor Inc., Icheon-si, Gyeonggi-do, Korea
- dHynix Semiconductor Inc., Ichon, South Korea
Papers open inside SciRah from the original publisher or repository; SciRah never hosts them.
Abstract
High-speed amplification from Josephson-level digital signals of a few millivolts to the volt levels employed in CMOS devices is optimally done in two stages. For the first stage we use a Josephson circuit which amplifies a few-millivolt input to several tens of millivolts. This drives a CMOS digital amplifier. The CMOS amplifier must be calibrated to compensate for random threshold voltage variations in the fabrication process; the design of a digital calibration circuit is included. Simulations of the calibrated amplifier at 300 K show a digital output of 1.8 V with a delay of 70-90 ps when fabricated in a 65 nm CMOS process. Simulations for 4 K will yield better results and are in progress.