A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
John Bartha b, William R. Reohrc d, Paul Parriese, Gregory Fredemane, John W. Golze, Stanley E. Schusterc d, Richard E. Matickc d, Hillery C. Hunterc d, Charles C. Tannera b, Joseph Hariga b, Hoki Kime, Babar A. Khane, John Griesemere, R.P. Havreluke, Kenji Yanagisawae, Toshiaki Kirihatae, Subramanian S. Iyere
- aIBM Burlington, Essex Junction, VT, USA
- b[IBM Burlington, Essex Junction, VT, USA]
- cIBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
- d[IBM Thomas J. Watson Research Center, Yorktown Heights, NY , USA]
- eIBM, NY, USA
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Abstract
As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods. To address the realities of process integration, we describe the features and issues associated with integrating this DRAM into SOI technology, including deep trench processing and floating body effects. After a brief description of the macro architecture, details are provided on the three-transistor micro sense amplifier scheme, which is key to achieving a high transfer ratio with minimal area overhead. The paper concludes with hardware results and a summary.