A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier
John Bartha b, William R. Reohrc d, Paul Parriese f, Gregory Fredemane f, John W. Golze f, Stanley E. Schusterc d, Richard E. Matickc d, Hillery C. Hunterc d, Charles C. Tannerb g, Joseph Hariga b, Hoki Kime f, Babar A. Khane f, John Griesemere f, R.P. Havrelukc d, Kenji Yanagisawae f, Toshiaki Kirihatae f, Subramanian S. Iyerf g
- aIBM, Burlington, VT, USA
- bIBM, Burlington, VT#TAB#
- cIBM T.J Watson, Yorktown Heights, NY, USA
- dIBM T.J Watson, Yorktown Heights, NY
- eIBM, Hopewell Junction, NY, USA
- fIBM,Hopewell Junction,NY
- gIBM, Hopewell Junction, NY
Papers open inside SciRah from the original publisher or repository; SciRah never hosts them.
Abstract
A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA). The macro was characterized via a test chip fabricated in a 65nm SOI deep-trench DRAM process. Measurements confirm 1.5ns random access time with a 1V supply at 85deg and low voltage operation with a 600mV supply.