Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching
Ioannis Voyiatzisa, Kyriakos Axiotisb c d, Nikolaos Papaspyroub c d, Hera Antonopouloue, Constantinos E. Efstathioue
- aDept. of Inf., TEI of Athens, Athens, Greece
- bSch. of Electr. &
- cComput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece
- dSch. of Electr. & Comput. Eng., Nat. Technol. Univ. of Athens, Athens, Greece
- eTEI of Patras, Greece
Papers open inside SciRah from the original publisher or repository; SciRah never hosts them.
Abstract
Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise unnaturally the power consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this paper, the utilization of gray code generators is proposed as a low-power BIST solution. More precisely, we show how the time required to apply a given test pattern can be decreased, by switching between different gray sequences during the application of the test set. Experimental results indicate that the time required to embed the test set within a low-power sequence is reduced to almost 50%, compared to a previously proposed solution.